3.3.3 Vertical SJ DMOSFETs

Vertical SJ DMOSFET were recently introduced both theoretically and commercially and achieved a significant improvement in the trade-off between $R_\mathrm{sp}$ and BV compared to conventional VDMOSFETs. Vertical SJ devices such as COOLMOS [31] and MDmesh [32] assume complete charge balance of the depletion layer. This can be achieved by introducing alternating

- and

-columns in the drift region, which allows to drastically increase the doping in this region. A series of multiple epitaxial depositions of lightly

-doped silicon on a highly doped

-substrate and related boron (and

or phosphor) implantation steps can be used for the fabrication of such vertical SJ devices. However, precise control of the mask steps is important for this process. Even the current conduction area is reduced by additional

-columns which do not contribute towards on-state conduction, which results in a significant reduction in $R_\mathrm{sp}$ of the devices by using a high doping concentration in the

-pillar.

**Figure 3.22:** Cross section of a SJ DMOSFET.
$\begin{figure}\begin{center} \psfig{file=figures/superjunction/SJ_MOS.eps, width=0.45\linewidth} \vspace{0.0cm} \end{center}\end{figure}$

Figure 3.22 shows a cross section of a SJ DMOSFET, which has a concept similar to a multi-RESURF idea. This structure allows a doping level of the

-region, which is typically one order of magnitude higher than that in standard high-voltage MOSFETs. The additional charge is counterbalanced by the adjacent charges of the

-column, thus contributing to a horizontal electrical field without affecting the vertical field distribution. The electric field inside the structure is fixed by the net charge of the two oppositely doped columns. Thus a nearly flat field distribution similar to that in SJ

-structures can be achieved, if both regions counterbalance each other perfectly.

For higher blocking voltages only the depth of the columns has to be increased without any change of the doping. This leads to a linear relationship between blocking voltage and on-resistance instead of the power relationship for the case of conventional VDMOSFETs. Considering the drift region of a SJ DMOSFET has a length $L_\mathrm{d}$ , the

- and

-column widths are $W_\mathrm{N}$

$W_\mathrm{P}$

$W_\mathrm{PN}$ , and the

- and

-column dopings are $N_\mathrm{A}$ and $N_\mathrm{D}$ , respectively, and assuming that the

- and

-pillars are completely depleted before breakdown and perfect charge balance of each column, the BV and the charge

of the column are given by

$\displaystyle \mathrm{BV} = E_\mathrm{c}\, L_\mathrm{d}\,,$

(3.41)

$\displaystyle Q = \frac{N_\mathrm{D}\,W_\mathrm{PN}}{2} = \frac{\varepsilon_{si}\,E_\mathrm{c}}{q}$

(3.42)

where the critical electric field $E_\mathrm{c}$ is also increased by the increased doping concentration of the pillar.

**Figure 3.23:** Comparison of the $R_\textrm {sp}$ versus BV for the CoolMOS and conventional power VDMOS transistors.
$\begin{figure}\begin{center} \psfig{file=figures/chapt3/compSJ-VDMOS.eps, width=0.68\linewidth} \end{center}\end{figure}$

Because the current flows only through the

-column, the specific on-resistance $R_\mathrm{on,sp}$ can be expressed as

$\displaystyle R_\mathrm{sp} = \frac{L_\mathrm{d}}{q\,\mu_n\,N_\mathrm{D}} = \frac{W_\mathrm{PN}\,\mathrm{BV}}{2\mu_n\,\varepsilon_{si}\,E^2_\mathrm{c}}\,.$

(3.43)

This equation clearly shows the linear relationship between the BV and the specific on-resistance of SJ DMOSFETs instead of the power relationship for the case of conventional DMOSFETs.

Figure 3.23 shows the $R_\mathrm{sp}$ comparison of the commercial COOLMOS and VDMOSFET [134]. $R_\mathrm{sp}$ of the conventional VDMOSFET increases sharply as a function of blocking voltage. COOLMOS (vertical super-junction MOS transistor) has a week linear relationship between $R_\mathrm{sp}$ and BV.

Practically the main advantage of SJ DMOSFETs is the drastic reduction of the device area because of its low specific on-resistance. This small chip size of the SJ DMOSFET leads to a low gate charge, which results in a short turn-on delay time compared to that of conventional DMOSFETs with comparable voltage and current ratings.