3.3 Super-Junction Concepts

The main issue in the development of power semiconductor devices is to obtain the best trade-off between the specific on-resistance $R_\mathrm{sp}$ and the BV, and to shrink the feature size without degrading device characteristics. Although much effort has been put into the reduction of $R_\mathrm{sp}$ while maintaining the desired BV, it has been understood that there is a limit [125]. Recently, the super-junction (SJ) concept was suggested and studied, which achieved a significant improvement in the trade-off between the on-resistance and the BV compared to conventional devices [126,127,128,129,130,131,132].

Figure 3.11 shows the published $R_\mathrm{sp}$ versus BV of four different device structures and their theoretical limits [15,133]. Note that these theoretical limits are only one part to estimate device performance, it is mainly related to the cost of the devices. Other aspects, such as parasitic capacitances, switching speed, thermal dissipation, and operation temperature are not considered in Figure 3.11.

**Figure 3.11:** Published $R_\textrm {sp}$ versus BV of four different device structures and their theoretical limits.
$\begin{figure}\begin{center} \psfig{file=figures/chapt3/onLim.eps, width=0.7\linewidth} \end{center}\end{figure}$

From this figure both SOI and super-junction structures have a best trade-off between $R_\mathrm{sp}$ and BV, and more improvements could yet be expected with the development of manufacturing technology. The theoretical limits for super-junction devices depend on the

- and

-column width of the drift region. Violet lines show the theoretical limit for the super-junction (vertical) structure with various column widths (2 $\times$ $W_\mathrm{N}$

2 $\times$ $W_\mathrm{P}$

5.0 $\mu$ m, 10.0 $\mu$ m, and 16.0 $\mu$ m, respectively), and lower $R_\mathrm{sp}$ is obtained with smaller column width. Doping concentration rises with decreasing column width, however, small columns become more and more difficult to produce. Lateral super-junction combination with SOI structure can be the one possible solution to overcome the process difficulties.