4.3.2 Device Structures and Operations

Figure 4.24 and Figure 4.25 show the schematic structures of a standard SJ LDMOSFET on SOI and a proposed lateral trench gate SJ SOI-LDMOSFET which are used for the simulation of the BV and the on-resistance, respectively. As shown in Figure 4.24, the standard SJ SOI-LDMOSFETs can be made by introducing extra $p$-columns in the drift region. It is assumed that the charge in the $n$- and $p$-column of the drift layer should be exactly balanced, and this is true only when the drift length of the device is large enough to ignore the effect of the charge in the $p$-body.

The device is designed to achieve a BV of 120V with an SOI thickness $t_\mathrm{soi}$ of 1.0$\mu$m and with a buried oxide thickness $t_\mathrm{ox}$ of 1.0$\mu$m. With the same $n$- and $p$-column width ( $W_\mathrm{N}$ and $W_\mathrm{P}$) of 0.5$\mu$m and a drift layer length of 6.0$\mu$m the doping concentration of the $n$-column $N_\mathrm{D}$ can be raised up to 9.9 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$. The extra $p$-column is doped to achieve a balanced charge condition which means that the net depletion layer charge is zero. As shown in Figure 4.25, the proposed lateral trench gate SJ SOI-LDMOSFET has a similar structure as that of a standard SJ SOI-LDMOSFET (see Figure 4.24) except that it has a trench gate on the side wall.

Figure 4.24: SJ LDMOSFET on SOI.

Figure 4.25: Proposed 120 V lateral trench gate SJ SOI-LDMOSFET and current flow iso-lines at $V_\textrm {GS}$ $=$ 12 V and $V_\textrm {DS}$ $=$ 10 V.

Together with the channel on the top of the SOI layer this allows to obtain an increased channel area compared to that of conventional SOI-LDMOSFETs. From Figure 4.25 it is clear that only the $n$-column of the drift region contributes to the current conduction in the on-state and the channel current flowing on the side wall of the trench can be seen. With the increased channel area a reduction of the channel resistance can be achieved.

An unbalanced structure which has larger $W_\mathrm{N}$ than $W_\mathrm{P}$ is used to examine the influence of charge imbalance on the on-resistance and the sensitivity of the BV. Because of the increased $n$-column width $W_\mathrm{N}$ from 0.5$\mu$m (in the case of SJ SOI-LDMOSFET in Figure 4.24) to 1.0$\mu$m the doping of this region is reduced to 6.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$ by employing SJ concepts.

The width, space, and depth of the lateral trench gate are 0.4$\mu$m, 1.1$\mu$m and 1.0$\mu$m, respectively. Simulations are performed for 120V lateral trench gate SJ SOI-LDMOSFETs with an $n$-column width $W_\mathrm{N}$ $=$ 2 $\times$ $W_\mathrm{P}$ of 1.0$\mu$m and doping $N_\mathrm{D}$ of 6.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$. The other structure parameters are the same as that in Figure 4.24.