5.1 Summary of Proposed Lateral Power Devices

We discussed the BV and temperature dependence of partial-SOI (P-SOI) LDMOSFETs in terms of different locations of the silicon window. Our simulations confirmed that the BV and self-heating effect of the P-SOI with the silicon window under the source is better than those of P-SOI with the silicon window under the drain. For the P-SOI LDMOSFET ( $t_\mathrm{soi}$ $=$ 7 $\mu$m and $t_\mathrm{ox}$ $=$ 2$\mu$m) with the silicon window under the drain, a maximum BV of 355V is obtained at $C_\mathrm{sub}$ $=$ 6 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ and $L_\mathrm{d}$ $=$ 25$\mu$m. For the P-SOI LDMOSFET with the silicon window under the source, a maximum BV of 397V is obtained at $C_\mathrm{sub}$ $=$ 3 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ and $L_\mathrm{d}$ $=$ 30$\mu$m. The improvement in the voltage handling capability was about 32% compared to conventional 300V SOI LDMOSFET. Since the voltage drops in the buried oxide and in the depletion layer of the substrate region, a higher BV is obtained in this structure compared to that of a P-SOI LDMOSFET with a silicon window under the drain.

A lateral trench gate LDMOSFET on SOI was proposed. This allows obtaining an increased channel area of the device. The channel current flows on the side wall of the lateral trench gate can be seen clearly in the three-dimensional simulation results. A lower specific on-resistance is obtained in the suggested structure compared to that of a conventional SOI-LDMOSFET. With a lateral trench gate our three-dimensional simulations confirm that it is possible to get the best trade-off between the BV and $R_\mathrm{sp}$ of the LDMOSFET on SOI. The specific on-resistance strongly depends on the trench depth. It decreases with increasing the trench depth. The space between the trenches weakly affects the on-resistance. Simulations are performed for the 100V lateral trench gate SOI-LDMOSFETs with an $n$-drift length $L_\mathrm{d}$ $=$ 5.5$\mu$m and a doping $N_\mathrm{D}$ $=$ 1.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$. With a lateral trench depth of 1.5$\mu$m a lower $R_\mathrm{sp}$ of 264m$\Omega$ mm $^\mathrm{-2}$ is obtained. This is about 8.3% smaller than the corresponding $R_\mathrm{sp}$ value of the conventional SOI-LDMOSFET.

A lateral trench gate SJ SOI-LDMOSFET transistor was proposed. A lower specific on-resistance is obtained in the suggested structure. Our simulations confirm that the $R_\mathrm{sp}$ of the lateral trench gate SJ SOI-LDMOSFETs is about 60% lower than that of conventional SOI-LDMOSFETs. This value is lower than that of a SJ SOI-LDMOSFET which has a much higher $n$-column doping of 9.9 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$. Unlike the standard vertical SJ devices, the optimum $p$-column doping of the SJ SOI-LDMOSFETs is lower than that of the $n$-column. For the SJ SOI-LDMOSFET with an $n$-column doping $N_\mathrm{D}$ of 9.9 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$, a maximum BV of 124V is obtained at $N_\mathrm{A}$ $=$ 6.5 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$. With $N_\mathrm{D}$ of 6.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$, a maximum BV of 127V is obtained at $N_\mathrm{A}$ $=$ 2.5 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$. Similar results are obtained for the lateral trench gate SJ SOI-LDMOSFET. Together with the larger width of the $n$-column than that of the $p$-column in the drift region it is possible to lower the doping of the $n$-column without degrading the on-resistance. As a result the sensitivity of the BV to the charge imbalance is reduced compared to that of the standard SJ SOI-LDMOSFET.

A high-voltage SJ SOI-LDMOSFET with a trench oxide in the drift region was proposed. A lower $R_\mathrm{sp}$ is obtained in the proposed device. The $R_\mathrm{sp}$ of the proposed device which has a drift length $L_\mathrm{d}$ $=$ 13.0$\mu$m, a $p$-column doping $N_\mathrm{A}$ $=$ 4.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$ and a $p$-column width $W_\mathrm{P}$ $=$ 0.3$\mu$m is 25.4m$\Omega$ $cm^2$. Even $L_\mathrm{d}$ is reduced to 13.0$\mu$m, the BV is the same as that of the conventional SOI-LDMOSFET with $L_\mathrm{d}$ $=$ 20.0$\mu$m. Our simulations confirm that the $R_\mathrm{sp}$ of the proposed device is about 76% and the $n$-drift length is about 65% of that of conventional SOI-LDMOSFETs, respectively. With this new device concept it is possible to reduce the device size and $R_\mathrm{sp}$ without degrading the BV.

We proposed a SOI SA-LIGBT which has a trench oxide at the drain/anode region. The $n^+$-drain and $p^+$-anode of the proposed device are separated by the trench oxide, which results in a higher pinchoff resistance under the $p^+$-anode. With this structure it is possible to suppress the NDR effectively without increasing the $p^+$-anode length. The snap-back voltage inherently present in the SA-LIGBT is about 20% lower than that of a conventional SA-LIGBT. Additionally, significant improvements in the turn-off time can be achieved by the shorted-anode structure.