The design and fabrication of semiconductor devices in modern integrated circuit technology rely crucially on the numerical simulation of fabrication processes and device behavior for achieving competitive cycle times and reducing development costs for Very Large Scale Integration (VLSI) products. Technology Computer Aided Design (TCAD) comprises all software tools, strategies, and methodologies that support the development and verification of semiconductor processes and devices.
This dissertation presents a TCAD environment for the simulation of complete VLSI fabrication processes that emphasizes tool integration, process-flow representation, and task-level automation. VISTA/SFC is based on the Vienna Integrated System for TCAD Applications (VISTA), a TCAD integration and development framework, and its Simulation Flow Control (SFC) module, extending concepts and mechanism found in VISTA towards the production use of the framework.
The integration of heterogeneous process and device simulation tools is realized by providing standardized interfaces between the a task control layer and external executables. External gridding tools are used to automatically ensure the consistency of the wafer model after each process simulation step. LISP functions are used to bind external executables to the environment. The Profile Interchange Format (PIF) is used as a primary wafer-data exchange format.
The representation of process flows is based on simulator-specific statements, with a mapping step being used to transform factory-specific and process-specific statements to appropriate tool calls. Execution of process flow experiments is done in parallel across the computing network, dynamic split-point generation minimizes the computation load. Robustness and easy of use have been major concerns in the design and implementation of the graphical user interface (GUI) for process flow definition, experiment control, and data management.
For the convenient definition and representation of more complex tasks, a class of objects has been added to the environment that encapsulate task-level applications like Design of Experiments (DoE), Response Surface Modeling (RSM), and optimization, and provide built-in data management and post-processing capabilities.
The applicability and usefulness of the implemented prototype is demonstrated by two examples. A complete CMOS fabrication process is simulated using a variety of heterogeneous simulation tools, and the encapsulation of a complex optimization task for the reduction of the short-channel effect on the threshold voltage of an NMOS transistor by means of an additional pocket implantation step is shown.