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- vos::tool
- 4.6.1 Configuration
- name=
- 8.3 EVE: Evaluable Entities
- name
- 8.3 EVE: Evaluable Entities
- define-control
- 8.3.1 Basic Functionality
- set-control
- 8.3.1 Basic Functionality
- set-control-expression
- 8.3.1 Basic Functionality
- set-control-conversion
- 8.3.1 Basic Functionality
- sequence
- 9.2.4 Task Definition
- parallel
- 9.2.4 Task Definition
- Agents
- 3.5.1 Encapsulation of External
- Batch file
- 3.3.1 Task Control Layer
- Batch-mode operation
- 6.7.3 Batch Mode Operation
- Berkeley Process Flow Language
- 5.4.1 PFR for Manufacturing
- Binding function
- 4.4.1 Binding Function
- Binding functions
- 3.3.3 Tool Binding
- BPFL
- 5.4.1 PFR for Manufacturing
- CAD methodologies
- 1.1 Semiconductor Technology
- Calibration
- 4.5 Simulator Calibration | 5.6.1 Mapping
- Callback mechanism
- B Callback Mechanism
- Case sensitivity
- 8.3 EVE: Evaluable Entities
- CFI
- 5.4.1 PFR for Manufacturing
- Client side
- 8.3 EVE: Evaluable Entities
- CMOS process
- 9.1 Standard CMOS Process
- Color-coding
- 6.6.1 Color Coding
- Computer-Integrated Manufacturing
- 1.1.2 CIM: Computer Integrated
- Concurrent clients
- 3.5 Concurrent Clients
- Concurrent engineering
- 10.5.2 Concurrent Design
- Conditional execution
- 8.4.1 Flow EVE
- Controls
- 8.3 EVE: Evaluable Entities
- Design
- 3.4.1 VISTA/SFC Graphical User
- Design space
- 8 Task Level TCAD
- Detached operation
- 6.7.3 Batch Mode Operation
- Electronic CAD
- 1.1.1 ECAD: Electronic Computer
- Epsilon
- 6.2 Experimental Splits
- Equipment step
- 5.3 OperationsSteps, and
- Evaluable Entity
- 8.3 EVE: Evaluable Entities
- EVE
- 8.3 EVE: Evaluable Entities
- EVI
- 8.5 EVI: Evaluation Instances
- Fabrication processes
- 5.1 Fabrication Process Steps
- Feature size
- 5.3 OperationsSteps, and
- File purging
- 7.1.2 Data Files
- Fit error
- 8.8 Optimization and Calibration
- Flow editor
- 3.3.2 Simulation Flow Control | 5.10 Graphical Flow Editor
- Hosts
- 3.4.1 VISTA/SFC Graphical User
- restricted
- 3.4.1 VISTA/SFC Graphical User
- Information models
- 4.3 Data Level
- Input deck template
- 4.4.3 Input Deck Templates
- Input" deck
- 4.4.3 Input Deck Templates
- Interface agents
- 3.3.3 Tool Binding
- Internet
- 10.5.5 Internet Collaboration and
- Layout
- 1.1.1 ECAD: Electronic Computer
- Layout data
- 5.11 Layout Data
- Libraries
- 5.7.4 Libraries
- LISP
- comment character
- A LISPXLISP, and
- function declaration
- A LISPXLISP, and
- nodes
- A LISPXLISP, and
- overview
- A LISPXLISP, and
- predicate" functions
- A LISPXLISP, and
- type information
- A LISPXLISP, and
- LISP expressions
- encapsulation
- 8.4.5 LISP EVE
- Load" balancing
- 3.4.1 VISTA/SFC Graphical User
- Manufacture acceptance
- 2.1.8 Design Centering and
- Matrix calibration
- 4.5 Simulator Calibration
- Model parameters
- 1.1.1 ECAD: Electronic Computer
- Modules
- 5.7.3 Modules
- Monte Carlo method
- 2.1.8 Design Centering and
- Non-positional parameter passing
- 5.9.1 File Format
- NORMAN
- 5.9 Programming Interface
- Operations
- 5.7.2 Operations
- Optimization
- global optimum
- 9.2.5 Optimization Result and
- initial values
- 9.2.5 Optimization Result and
- Orphaned run
- 7.2 Splitting and Data
- Parameter selection
- 8.4.1 Flow EVE
- Parameterized design
- 8.1 Design Parameterization and
- PIF Application" Interface
- 3.3.1 Task Control Layer
- Pifcopy
- C Auxiliary PIF Tools
- Pifmaid
- C Auxiliary PIF Tools
- Pifrm
- C Auxiliary PIF Tools
- Pifstat
- C Auxiliary PIF Tools
- Planar technology
- 5 Semiconductor Process Flow
- Process flow
- 5.3 OperationsSteps, and
- Process flow representation
- 5 Semiconductor Process Flow
- Process operation
- 5 Semiconductor Process Flow
- Process simulation tools
- 5.2 Process Simulation Tools
- Process step
- 5.3 OperationsSteps, and
- Profile Interchange Format
- 3.3.1 Task Control Layer
- Project
- 3.4.1 VISTA/SFC Graphical User | 6.1 Projects
- Proprietary procedures
- 5.4 Process Flow Representations
- Recipe
- 5.3 OperationsSteps, and | 5.4 Process Flow Representations | 5.7.2 Operations
- Resource
- 4.4.2 Tool Resources
- boolean
- 4.4.2 Tool Resources
- Resources
- 3.4.1 VISTA/SFC Graphical User
- Responses
- 8.3 EVE: Evaluable Entities
- Rework
- 6.5.4 Rework
- RSM-EVE calibration
- 8.4.3 RSM EVE Calibration
- Run controller
- 3.3.2 Simulation Flow Control
- Run data base
- 3.3.2 Simulation Flow Control
- Run traveler
- 5.3 OperationsSteps, and
- Screening analysis
- 8.6 Design of Experiments
- Semiconductor equations
- 1.1.3 TCAD: Technology Computer
- Server side
- 8.3 EVE: Evaluable Entities
- Short channel effect
- 5.11.1 Variational Masks | 9.2 Short Channel Effect
- Simulation Flow Control
- 3.2.1 Simulation Tool Integration
- Simulation stages
- 4 Integration of Simulation
- Single-step operation
- 6.5.2 Single Step Operation
- Socket
- 6.7.3 Batch Mode Operation
- Split branch
- 6.2 Experimental Splits
- Split parent
- 6.2 Experimental Splits | 7.2 Splitting and Data
- Split point
- 6.2 Experimental Splits
- Split-lot experiments
- 3.3.2 Simulation Flow Control
- SPR
- 5.4.1 PFR for Manufacturing
- Spread sheet
- 8.5 EVI: Evaluation Instances
- Static calibration
- 4.5 Simulator Calibration
- Steps
- 5.7.1 Steps
- Stop and resume
- 6.5.3 Stop and Resume
- Supplementary design
- 8.6 Design of Experiments
- System jobs
- 3.4.1 VISTA/SFC Graphical User
- System Tool Interface
- 4.6 System Tool Interface
- Task
- 8 Task Level TCAD
- Task control layer
- 3.3.1 Task Control Layer
- Task level
- 8 Task Level TCAD
- Task-level services
- 3.3.1 Task Control Layer
- TCAD frameworks
- 1.1.3 TCAD: Technology Computer
- Technology CAD
- 1.1.3 TCAD: Technology Computer
- Temporary data
- 8.5 EVI: Evaluation Instances
- Threshold voltage
- 9.2.1 Threshold Voltage Reduction
- TIF format
- 4.3.2 Native Tool Formats
- Tool agents
- 5.6.1 Mapping
- Tool application
- 4.1.3 Tools and Tool
- Tool application layer
- 3.3.3 Tool Binding
- Treatment
- 5 Semiconductor Process Flow
- Triangle
- 4.3.4 Gridding
- gridding parameters
- 4.3.4 Gridding
- Variational design
- 8.1 Design Parameterization and
- Variational masks
- 5.11.1 Variational Masks
- VISTA
- 1.2.1 The VISTA Project
- VLISP
- 3.6 Implementation of VISTA/SFC | A LISPXLISP, and
- VLISP" interpreter
- 3.3.1 Task Control Layer
- VOS - Vienna Operating System
- 3.6 Implementation of VISTA/SFC
- VUI - Vienna User Interface
- 3.6 Implementation of VISTA/SFC
- Wafer state model
- 4.3.1 PIF: Profile Interchange
- Wafer state" model
- 4.3 Data Level
- World Wide Web
- 10.5.5 Internet Collaboration and
- XLISP
- A LISPXLISP, and
- Yield
- 5.1 Fabrication Process Steps
Christoph Pichler
Thu Mar 13 14:30:47 MET 1997