5.4.2 Actual Device

The device is a standard N-channel MOS-transistor with an LDD-implant. The geometry of the device and the doping profiles are assumed to be symmetric. This reduces the number of variables for the source and drain well regions.

The actual device generated by the analytical device generator is shown in Figure 5.15. On top is the gate oxide with the poly gate contact, the source and drain spacers and the source and drain contacts itself.

The doping regions are modeled using:

Source and drain wells: The source and drain wells are modeled by two Pearson/Error-function distributions.

• The S/D 1 source-drain well is implanted using the gate mask.
• The S/D 2 source-drain well is implanted using the spacer as mask.

The second implant has a higher maximum than the first one.

Channel implant: two superposed purely vertical profiles

• The C 1 implant is a shallow channel implant modeled by a vertical Pearson/Error-function.
• The C 2 implant uses a vertical Gaussian profile.