5.1.3 Simulation Flow of the Device Structure

In contrast to the standard VDMOS transistor not two separate elements of p-dopants but two implantation masks are used instead to build the region with the reduced gradient under the gate. The simulation flow of the device is listed in Table 5.1. For the simulation of the fabrication process the programs SKETCH, promis-Implant [52], the commercial tool Tsuprem4 [58], and, for the electrical characterization, MINIMOS-NT [48] were used. The simulation flow is tuned for a short computation time but adequately represents the electrical characteristics of the device.

Table 5.1: Simulation flow of the the VDMOS transistor.

Process Step	Tool	Settings
Substrate	sketch	Boron, $1 \cdot 10^{10} \ {\rm cm}^{-3}$, thickness $2.0 \ {\rm\mu m}$
Epi-layer deposition	sketch	Phosphorus, $1.45 \cdot 10^{15} \ {\rm cm}^{-3}$, thickness $10.5 \ {\rm\mu m}$
Oxide deposition	sketch	SiO2, thickness $0.85 \ {\rm\mu m}$
Lithography	sketch
Strip Resist	sketch
p- implantation	promis	Boron, $80 \ {\rm keV}$, $1 \cdot 10^{13} \ {\rm cm}^{-2}$
Lithography	sketch
Strip resist	sketch
p+ Implantation	promis	Boron, $45 \ {\rm keV}$, $5 \cdot 10^{14} \ {\rm cm}^{-2}$
Strip Resist	sketch
Strip Oxide	sketch
Gate oxide	sketch	SiO2, thickness $0.05 \ {\rm\mu m}$
p diffusion	Tsuprem4	$1100^{\circ}$, $200 \ {\rm min}$
p diffusion	Tsuprem4	$1100^{\circ}$ to $800^{\circ}$, $150 \ {\rm min}$
Gate poly deposition	sketch	Poly, thickness $0.5 \ {\rm\mu m}$, Phosphorus $1 \cdot 10^{15} \ {\rm cm}^{-3}$
Lithography	sketch
Strip resist	sketch
Source doping implantation	promis	Arsenic, $120 \ {\rm keV}$, $5 \cdot 10^{15} \ {\rm cm}^{-3}$
Oxide deposition	sketch	SiO2, thickness $1 \ {\rm\mu m}$
Arsenic diffusion	Tsuprem4	$800^{\circ}$ to $1000^{\circ}$, $20 \ {\rm min}$
Arsenic diffusion	Tsuprem4	$1000^{\circ}$ to $800^{\circ}$, $100 \ {\rm min}$
Lithography	sketch
Strip Resist	sketch
Etch recess	promis
Source contact deposition	sketch	Aluminum, thickness $2 \ {\rm\mu m}$