2.8.1 Fabrication and Performance of CNT-FETs

The first CNT field effect transistors (CNT-FETs) were reported only a few years after the initial discovery of CNTs [4,3]. These early devices, shown schematically in Fig. 2.14-a, were relatively simple in structure: Noble metal (gold or platinum) electrodes were lithographically patterned atop an oxide-coated, heavily doped silicon wafer, and a single-walled CNT was deposited atop the electrodes. The metal electrodes served as the source and drain, and the CNT was the active channel. The doped substrate served as the gate electrode, separated from the CNT channel by a thick ( $\sim 100-200~\mathrm{nm}$) oxide layer. These devices displayed clear p-type transistor action, with gate voltage modulation of the drain current over several orders of magnitude. The devices displayed high parasitic resistance ( $\geq 1~\mathrm{M\Omega}$), low drive current, low transconductance ( $g_m\sim 1~\mathrm{nS}$), high sub-threshold slope ( $S = {[d(\mathrm{log_{10}}I_\mathrm{d})/dV_\mathrm{g}]}^{-1}\sim 1~\mathrm{V/decade}$), and no current saturation. Due to the thick gate dielectric, these devices required large values of the gate voltage (several volts) to turn on, making them unattractive for practical applications.

Figure 2.14: a) Schematic structure of first CNT-FETs, with CNT draped over metal electrodes. b) Improved CNT-FET structure, with metal electrodes deposited upon the CNT, followed by thermal processing to improve contact. The substrate serves as the gate for both device structures, and it is separated from the CNT by a thick oxide layer.

Following these initial results, advances in CNT-FET device structures and processing yielded improvements in their electrical characteristics. Rather than laying the CNT down upon the source and drain electrodes, relying on weak VAN DER WAALS forces for contact, the CNTs were first deposited on the substrate, and the electrodes were patterned on top of the CNTs, as shown in Fig. 2.14-b. In addition to Au, Ti and Co were used [63,64,65] with a thermal annealing step to improve the metal-CNT contact. In the case of Ti, the thermal processing leads to the formation of TiC at the metal-CNT interface [64], resulting in a significant reduction in the contact resistance from several $\mathrm{M\Omega}$ to $\sim\mathrm{30~k\Omega}$. On-state currents $\sim \mathrm{1~\mu A}$ were measured, with a transconductance of $\sim \mathrm{0.3~\mu S}$ -- an improvement of more than two orders of magnitude relative to the VAN DER WAALS contacted devices. This CNT-FET device configuration has been extensively studied in the literature. More recently, it has been found that Pd forms a low resistance contact to CNTs for p-type devices [66]. It is speculated [66] that Pd offers improved sticking or wetting interaction to the CNT surface relative to other metals, as well as good FERMI level alignment relative to the CNT conduction band. This point will be explored further in Section 2.8.2.

Figure 2.15: Schematic cross-section of top-gate CNT-FET.

As mentioned above, early CNT-FETs were p-type in air (hole conduction). The role of the ambient on CNT-FET conduction will be discussed in Section 2.8.3, however, it was found that n-type conduction could be achieved by doping from an alkali (electron donor) gas [67] or by thermal annealing in vacuum [64]. In addition, it is possible to achieve an intermediate state, in which both electron and hole injection occur, resulting in ambipolar conduction [64]. The ability to controllably fabricate both p-type and n-type CNT-FETs is a key to the formation of complementary metal oxide semiconductor (CMOS) logic circuits.

Figure 2.16: Electrical characteristics of the CNT-FET shown in Fig. 2.15 for both top-gate and bottom-gate operation. The oxide thicknesses for the top-gate and the bottom-gate are 15 nm and 120 nm, respectively. Output characteristics for a) top-gate and b) bottom-gate operation. c) Transfer characteristics [68].

Early experiments on CNT-FETs were built upon oxidized silicon wafers, with the substrate itself serving as the gate and a thermally grown oxide film, typically $\sim 100~\mathrm{nm}$ or thicker, serving as the gate dielectric. The thick gate oxide required relatively high gate voltages ( $\sim 10~\mathrm{V}$) to turn on the devices, and the use of the substrate as the gate implied that all CNT-FETs must be turned on and off together, precluding the implementation of complex circuits. A more advanced CNT-FET structure [68] is shown in Fig. 2.15. The device comprises a top-gate separated from the CNT channel by a thin gate dielectric. The top-gate allows independent addressing of individual devices, making it more amenable to integration in complex circuits, while the thin gate dielectric improves the gate to channel coupling, enabling low voltage operation. In addition, the reduction of the capacitance due to gate-source and gate-drain overlap suggests that such a device structure would be appropriate for high frequency operation. Such a CNT-FET can also be switched using the conductive substrate as a bottom gate, allowing for direct comparison between top and bottom gate operation. Comparison of the output characteristics for top and bottom-gate operation of the device in Fig. 2.15 are shown in Fig. 2.16-a and Fig. 2.16-b, respectively. Operating the device with the top-gate yields distinctly superior performance relative to bottom gate operation, with a lower threshold voltage ( $\mathrm{-0.5 V}$ vs. $\mathrm{-12 V}$) and higher transconductance ( $\mathrm{3.25~\mu S}$ vs. $\mathrm{0.1~\mu S}$). Figure 2.16-c shows superior sub-threshold behavior for top-gate operation with an order of magnitude improvement in sub-threshold slope (130 mV/decade vs. 2V/decade).

In order to gauge whether or not CNT-FETs have potential for future nano-electronic applications, it is important to compare their electrical performance to those of advanced silicon devices. WIND et al. [68] demonstrated that although the device structure is far from optimized, the electrical characteristics, such as the on-current and the transconductance of the device shown in Fig. 2.15 exceeds those of state-of-the-art silicon MOSFETs. Further enhancements to CNT-FET structures, such as the use of high dielectric constant gate insulators [69,70], and additional improvements in the metal-CNT contact resistance at the source and drain [66] have lead directly to improved CNT-FET performance. Such improvements can be also applied to n-type CNT-FETs [71].

M. Pourfath: Numerical Study of Quantum Transport in Carbon Nanotube-Based Transistors