This work is dealing with two-dimensional process simulation in multi-layered nonplanar structures and can be seen as part of ongoing research in the field of process simulation at the Institute for Microelectronics [Pic85b] [Wim93] [Sti93a] [Str94].
In Chapter 2 we give a description of the Analytical Ion Implantation method used to simulate the implantation process by means of statistical moments. For this purpose probability weighted moments (PWM) are employed the first time in process simulation. To obtain two-dimensional doping profiles a convolution method is used.
In Chapter 3 the basic diffusion mechanisms in various semiconductor materials are discussed. Starting with the interstitial and vacancy mechanism in silicon including a detailed description of the point-defect interactions with dopants, we give a detailed description of the diffusion in polycrystalline silicon material, including the morphology and fabrication processes involved. We close this chapter with the diffusion properties of dopants within oxides and silicides.
In Chapter 4 the possibilities for solving the diffusion equations using the box integration method are presented. We would also like to address the problems arising with grid generation. Within this chapter the structure and design of the new diffusion simulation module PROMIS-NT (PROcess Modeling In Semiconductors Number Two) is given. Commencing with the box integration method used for the discretization of the diffusion equation, we continue with the library of diffusion and interface models built in. Also the validity and reliability of the models is demonstrated by simulations.
In Chapter 5 we present applications. We used the process
simulation tools and models developed within this work to show the
applicability of these models. The first example is the fabrication of a
single poly bipolar emitter structure, where the emitter profile is
fabricated by outdiffusion from a polysilicon layer. As a second example we
give the whole process flow and simulation results for the fabrication of a
BiCMOS device.
Finally, Chapter 6 suggests some future activities.