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1.1 Process Technology

The steady growth of the semiconductor market was made possible by steady advances in process technology. These advances on their part were driven by the need for increasing the density of components as postulated by Moore's Law. The key issue for the higher integration density was tackled by reducing the size of the components by means of improved pattern transfer carried out with lithography and etching techniques. Thereby lithography is the decisive factor for the achievable lateral integration, since its resolution determines the smallest feasible feature size, also called critical dimension (CD). For complementary metal-oxide semiconductor (CMOS) ICs which constitute 75% of the world's semiconductor consumption, the gate length is the CD and denominates each generation of process technology. Names like quarter-micron, 0.18$\mu\mathrm m$, 0.13$\mu\mathrm m$, and 0.10$\mu\mathrm m$ technologies not only denote the CD producible by the applied lithography technique but equally stand for the technology of all other process steps involved in the fabrication of a corresponding device. The process steps can roughly be classified in three groups:

Lithography addresses exposure equipment, resist materials and processing, as well as mask making and mask materials. It transfers the patterns defined in the design of the circuit onto the wafer.

Front end processes include thermal/thin films, oxidation, and doping as well as front end etch (plasma etching of the moat, trench isolation, and gate structures). These steps define the regions for the single components, isolate them from each other, define the doping and thus the electric function of the cells, and the contact areas.

Interconnects, also known as back end processes, finally focus on planarization, metals, dielectrics, and etch. These steps are used to connect the components with each other for defining the complex functionality of the IC, to isolate the single lines within and between the layers, and to connect the IC to the contact pads for the following packaging and assembling.

Several times the validity of Moore's Law seemed to expire since the resolution $W$ achievable with optical lithography approached its physical limit determined predominantly by the actinic wavelength $\lambda$

$$W = k_0 \frac{\lambda}{\mathit{NA}}.$$ (1.1)

Nevertheless the resolution could continuously be increased not only by developing light sources and resist systems for shorter wavelengths but also by optimizing the technological parameters which influence $k_0$ in the equation above. Various resolution enhancement techniques like optical proximity correction (OPC) and phase-shifting masks (PSM) as well as in-lens filtering and advanced illumination schemes reduced the smallest feasible feature size by tuning the values of $k_0$, the characteristic constant of a specific lithography process and $\mathit{NA}$, the numerical aperture of the illumination system [31].

Lately lithography seems to be superseded from its major position. Not because it is losing importance -- it still is the predominant factor when talking about pattern density in plane -- but because other aspects are gaining influence. Integration has been expanded to the vertical dimension of the silicon wafer, e.g., by deep trench capacitors for small area dynamic random-access memory (DRAM) cells. Together with lithography which defines the size of the trench cell at the wafer surface new etching technologies which are able to transfer this pattern with high directionality downwards into the substrate have significantly contributed to the introduction of new design rules. This goes hand-in-hand with shrinking sizes for contacts. Smaller contacts not only require strongly anisotropic opening formation techniques but also leakage-free barrier layer formation and voidless filling of the contacts demanding more sophisticated deposition techniques.

Moreover the higher density of the components also gave rise to more complex interconnect schemes with most recently up to 6 metal layers [57], consisting of different material stacks for the different layers. These metalization and contact technologies were necessary in order to fulfill the requirements of the complicated interconnect networks and multi-level connection schemes which already absorb more than half of the chip fabrication process budget. In comparison with the basic electric functionality of the device determined by the characteristic doping profiles obtained with combined process flows of mask, ion implantation and diffusion steps, the resistive, heat, capacitive, inductive, and cross-talk characteristics of the interconnects gain more and more influence on the chip design. Together with more complex device layouts and three-dimensional devices this challenges new innovations in process technology, forcing engineers to go to the operational limits of their machines and to find new solutions with new equipment.

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