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4.1.1 Examples
For the following two examples, the polygons of the mask layers were drawn with
PED. The geometries for the examples which combine the process recipe with the
layout of the structures are generated by means of a non-interactive
simulation controlled by a flow description and demonstrate the generation of a
DRAM cell and an interconnect structure with two metal layers.
Subsections
Prev: 4.1 Usage of Layout
Up: 4.1 Usage of Layout
Next: 4.1.1.1 DRAM Cell
W. Pyka: Feature Scale Modeling for Etching and
Deposition Processes in Semiconductor Manufacturing