5.1.5 Device Simulation and Process Variations

As an example Fig. 5.5 shows the sensitivity analysis of $\vert S_{\mathrm {21}}\vert^2$ towards changes of the critical parameter ${\it d}_\mathrm{gc}$. It is changed in 1 nm steps, thus this effect on the available gain at ${\it f}$= 80 GHz for this device is strong. A variation from nearly 0 dB to 5 dB can be observed.

From such an estimate for an InAlAs/InGaAs HEMT it is found that the maximum device speed possible in a HEMT is limited by process variations. When scaling the HEMT aspect ratio considerations require a similar scaling of the gate-to-channel separation [13,14]. This results as effective charge control and the effective gate length ( ${\it l}_{\mathrm{g}}$ + 2 ${\it d}_\mathrm{gc}$) are affected. This consideration for the gate-to-channel separation ${\it d}_\mathrm{gc}$ obeys a similar scaling law as the oxide thickness in a Si MOSFET. For gate lengths ${\it l}_{\mathrm{g}}$$\leq$ 100 nm gate-to-channel separations ${\it d}_\mathrm{gc}$$\leq$ 10 nm are required [87]. Since the ${\it d}_\mathrm{gc}$ variations $\Delta{\it d}_\mathrm{gc}$ within the process are estimated to be fixed $\Delta{\it d}_\mathrm{gc}$= 1-2 nm and gate length independent from analysis of wafer maps, a minimum value for ${\it d}_\mathrm{gc}$ is required, as for ${\it d}_\mathrm{gc}\leq$ 8 nm gate currents ${\it I}_{\mathrm{G}}$ increase significantly due to tunneling. Thus, scaling and device speed is limited from process variations, unless effective measures are found to increase the Schottky barrier height or reduce tunneling.