As an example Fig. 5.5 shows the sensitivity analysis of
towards changes of the critical parameter
. It is changed in 1 nm steps, thus this effect on the
available gain at 
= 80 GHz for this device is strong. A
variation from nearly 0 dB to 5 dB can be observed.
From such an estimate for an InAlAs/InGaAs HEMT it is found that the maximum device
speed possible in a HEMT is limited by process variations. When scaling the HEMT aspect ratio
considerations require a similar scaling of the gate-to-channel separation [13,14].
This results as effective charge control and the effective gate length (
+ 2
) are
affected.
This consideration for the gate-to-channel separation
obeys a similar scaling law as the
oxide thickness in a Si MOSFET. For gate lengths
100 nm gate-to-channel
separations
10 nm are required [87]. Since the
variations
within the process are estimated to be fixed
= 1-2 nm and gate length
independent from analysis of wafer maps, a minimum value for
is required, as for
8 nm gate currents
increase significantly due to tunneling.
Thus, scaling and device speed is limited from process variations, unless effective
measures are found to increase the Schottky barrier height or reduce tunneling.