1.1.3 Interconnects in Integrated Circuits

In general, as a consequence of the Moore's law, the continuous device scaling implies reduced cost per transistor, increased operating speed, and lower power consumption [47]. From this point of view, the interconnect wires, manufactured during the BEOL processing, play a key role.

The main goal of the metal wiring in an IC is to create electrical connections among the active devices in order to transmit and distribute signals and power across the circuit. Due to the shrinking and high signal speed requirements of modern ICs, the interconnect structures are becoming the bottleneck for delay and noise in chips, making the metal interconnect an obstacle for increasing IC speed and performance [122]. The characteristic RC delay of the interconnect is given by the product of its resistance (R) and capacitance (C) and is quadratic in proportion to its length. As the chip feature sizes are reduced, the capacitance between neighboring wires enhances along with the interconnect resistance, leading to a sharp increase in the RC delay [6]. A variety of methodologies at the material and design levels have been adopted to reduce interconnect RC delay, noise, and power consumption.

The introduction of new materials at the BEOL manufacturing stage can help to improve the chip performance. Innovations were made to the materials used for both the metal wires and the dielectric insulation in order to meet conductivity requirements and reduce the dielectric permittivity [6]. The replacement of aluminum as an interconnect metal with pure copper contributed to a reduction in the interconnect RC delay and, in turn, an increase in the IC speed; copper has a lower resistivity compared to aluminum resulting in an improved chip performance. Furthermore, its higher electrical conductivity, when compared to aluminum, leads to better resistance to electromigration phenomena. However, the transition to copper as a metal conductor was not sufficient for a significant decrease in RC delays. For this purpose, new insulating materials with lower dielectric permittivity (κ) than silicon dioxide are needed for wire insulation as the chip scales further in size.

The different interconnect-related problems described above can be considerably mitigated by employing innovative architectures and design approaches [122]. The use of multi-interconnect architectures, obtained by the stacking of more metal layers with different cross sections, is useful means to manage the interconnects' characteristics, such as a decrease in the resistance and power consumption. Furthermore, the introduction of repeaters within the interconnect and the use of interconnect shielding techniques can improve the propagation of the signal along the line and mitigate the resulting noise.

Despite the numerous benefits of these new designs, the primary concern of the interconnect today remains the length of the wire with respect to its cross-section. A long wire with a small cross-section results in a high resistance. Novel design solutions are required to provide better connections among devices within the chip.