6. Summary and Outlook

Moore's law has been a key indicator of the miniaturization trend of the transistor feature size for many decades. Since the continuous shrinking of transistor feature sizes and interconnect dimensions are approaching their physical limitations, Moore's law is expected to no longer be the main driving force for IC performance improvement. Alternative research directions for technological developments have been introduced to advance IC performance beyond only feature size scaling. One of those research domains, dubbed "More than Moore", has gained importance in recent years. It consists of the heterogeneous integration of multiple non-digital functionalities, such as sensors and MEMS, into devices and contributes to the functional diversification of technologies in a single package which do not scale according to Moore's law. A prominent strategy to continue along this trend is enabled through 3D integration technology. 3D integration is a new design paradigm which is based on the process of vertically stacking multiple functional technologies located at different planes of the chip and forming electrical connections between them, either through the silicon die or through the multilayer interconnect with an embedded die. Since the communication between the stacked sections of the chip requires vertical interconnections, a number of new interconnect designs have been introduced into the existing fabrication process flow to make 3D integration a reality, such as TSVs and solder bumps. Although 3D interconnects present distinct advantages, several reliability concerns, introduced from the fabrication process as well as from the device operating conditions, still occur in these emerging technologies. Electromigration-induced failure has been one of the main reliability issues in interconnects for 3D integration technologies since its potential degradation mechanism in metallization of ICs is initiated by the transport of atoms due to the high current density which passes through the metal film. Electromigration becomes a limiting factor for high current density flow in interconnects because it affects the long term interconnect behavior. As a consequence, more reliable interconnects, resistant against electromigration damage, must be developed in order to improve the technology lifetime.

The aims of this work were to investigate the physical mechanisms behind the electromigration induced degradation which influence the device lifetime and, consequently, its reliability. Traditionally, accelerated electromigration testing has been used to predict the electromigration lifetime of an interconnect. These experimental tests demand time, are expensive, and must be designed very carefully in order to ensure meaningful results for reliability evaluation. The use of modeling and simulation of the electromigration phenomenon is an alternative tool to aid in the design and fabrication of reliable metallizations and to understand the electromigration failure mechanisms with less time and cost than the experimental alternative. In this context, a description of the state-of-the-art modeling of electromigration was presented in detail, identifying its main advantages and weaknesses. The history of electromigration modeling has been treated starting from Black's equation to modern continuum models. Based on this groundwork, a fully 3D mathematical model for electromigration has been provided by taking into account the wide variety of physical effects which must be considered for the electromigration problem. Generally, electromigration modeling and simulation constitutes a multiphysics problem which can be separated into two main phases, namely, the early phase of void nucleation and the late phase of void evolution. During the first phase, the material transport caused by electromigration leads to a significant increase in the mechanical stress at those locations in the interconnect where the adhesion between the conducting metal and the surrounding material is weak. The build-up of mechanical stress induces the nucleation of voids inside the interconnect line. The second phase of failure involves the evolution of the void inside the metallization. During this phase, the mechanism of void growth leads to extremely large changes in the interconnect resistance until reaching a maximum value which does not fully interrupt the IC operation. The lifetime of the interconnect is then determined as the time needed to achieve the maximum critical value tolerable for a given circuit. The two-phase model equations were derived and numerically described using the finite element method. Then, the mathematical model for electromigration was implemented in a commercial TCAD tool which allows one to carry out numerical simulations. Electromigration simulations were performed for different case studies including an open TSV, a solder bump, and a corner interconnect with a defined microstructure. The devices vary in the way the electromigration failure is triggered.

Electromigration reliability was assessed for an open TSV structure, which represents one of the emerging interconnect technologies employed for 3D integration. For this purpose a two-step approach based on the full electromigration model has been employed. In the first step, the locations with the highest probability of void nucleation were identified by monitoring the stress build-up due to electromigration in the structure. Simulation results have shown that vacancy accumulation and the consequent development of mechanical stress are recognized to be close to the interface between the copper line and titanium nitride layer at the TSV bottom. This interface acts as an electromigration blocking boundary which stops the vacancy flux at the barrier layer. Therefore, vacancies accumulate at this location and lead to volume contraction of the structure resulting in the build-up of tensile stress. The electromigration void nucleation time is the time necessary to reach the threshold stress value for void nucleation. Assuming a critical stress in the order of 300MPa, the void nucleation time obtained for the case study varies between approximately one year and 80 days under accelerated conditions of current density from 1MA/cm² to 2.2MA/cm², respectively. The second step of the analysis is characterized by the evolution of the void. Two methodologies have been employed in order to investigate resistance change due to the dynamics of void evolution in an open TSV structure. First, a diffuse interface method was developed to numerically study the time evolution of voids under electromigration in the open TSV structure. The second method consisted in the derivation of a semi-empirical analytic model based on the void radius dependence of the incoming vacancy flux due to electromigration to describe the time needed to grow a void of a given volume. A small initial void was placed at the void nucleation site, and its evolution was tracked, including the current-crowding effect and the resistance increase. When a current loading is applied to the edge of a conducting metal line, the electromigration force leads to the growth of the void, which spans the line, and triggers electrical failure. It has been shown that the electromigration driving force increases the void by feeding its surface with vacancies. From the simulation, it was determined that current crowding is more pronounced when the void becomes larger. As a result, interconnect resistance grows sharply as the line nears a failure. Interconnect resistance changes in time until it reaches the common failure criterion of a 20% increase in resistance. Electromigration void evolution time is related to the time elapsed until this value is reached. The void evolution time is at about the same order of magnitude as the void nucleation time, which suggests that both stages, void nucleation and void evolution, are important to determine the open TSV's time-to-failure. Once both void nucleation and void evolution times were obtained, the evaluation of the complete electromigration lifetime was completed and the results were fitted to Black's equation. A comparison of the simulation results with Black's equation revealed that the model based on the combination of kinetics of void nucleation and void evolution provides a good tool for the estimation of electromigration TTF in open copper TSV structures.

Another case study of particular interest was a flip-chip solder bump technology. A key feature of this structure is that electromigration failure is primarily determined by the void nucleation mechanism combined with the formation of an IMC at the interface between the Sn solder bump and the Ni UBM layer. Therefore, electromigration analysis was carried out by using the model describing void nucleation in order to simulate the mechanical stress build-up driven by the dynamics of vacancies in the solder bump. From the simulation results, the location of void nucleation was identified close to the interface between the solder and UBM layer. Furthermore, this location was also observed to be the region of current crowding. When a threshold stress in the order of 8MPa was reached at this site, the time necessary to nucleate a void was estimated in the range between 7 hours and 1 hour under stress conditions of current density from 0.003MA/cm² to 0.008MA/cm², respectively. The scope of this study was the development of an analytical compact model for the estimation of the lifetime of the solder bump. The compact model was designed by an adaptation of the Korhonen's model and it was calibrated through a comparison with the TTF/current density curves obtained from the simulation analysis. The developed compact model allows for the prediction of the void nucleation time and thereby provides a convenient method for the evaluation of the solder bump lifetime.

An original study regarding the impact of current crowding and microstructure on the electromigration damage was carried out. The analysis of electromigration failure was performed on two different interconnect geometries: a linear interconnect and an angled (or L-shaped) interconnect. The L-shaped geometry produced a high current crowding close to the corner of the structure and consequently an increased material transport induced by electromigration. This result suggests an increased electromigration degradation in the presence of right angles in the interconnect. However, experimental observations showed that no voids have been nucleated directly in the interconnect corner, but voiding appeared at random locations along the metal line. The inclusion of material interfaces and grain boundaries as paths of higher vacancy transport in the electromigration model was useful to explain some experimental observations of electromigration-induced voiding in the given interconnects. Simulations produced peaks in vacancy concentration and mechanical stress dynamics at the triple points formed by the intersection between the material interfaces and grain boundaries. Since triple points were considered to be sites capable of trapping and releasing vacancies, it was shown that void nucleation materialized at those locations, away from the cathode end of the line. This analysis demonstrated that electromigration voiding was not determined by the presence of current density divergence at the interconnect corner, but by the influence of the interconnect microstructure. Furthermore, assuming a threshold stress value for void nucleation of 200MPa, a failure occurred after operating under accelerated conditions for 2 hours and 100 minutes in the case of the straight and L-shaped geometries, respectively, when a current density of 4MA/cm² was applied. This leads to the conclusion that, even if a small difference in time between the two simulated structures is observed, the comparative study provided a qualitative estimation of their lifetimes.

The results obtained from the simulations of electromigration failure in the different case studies demonstrated the validity and capabilities of the TCAD electromigration model for the prediction of the electromigration lifetime of modern interconnects for 3D integration technology. In spite of the successful realization of interconnects for 3D integration and well-proven simulation models, further improvements should be considered both in the fabrication process as well as physical modeling. During the fabrication process, metal lines are deposited and covered with a passivation layer at a high temperature. Due to the large difference in thermal expansion coefficients between the metal line and surrounding material, a significant thermal stress is induced in the conducting line, when it is cooled to room temperature. In addition, the influence of a residual stress on the nucleation and propagation of voids in the metal line is present even in the absence of electric current and, therefore, electromigration. These stresses must be included in the simulation procedure. Future studies concerning the development of the electromigration model should address the extension of the void evolution model by including the gradient in electromigration-induced, thermal, and residual stress build-up as additional driving forces for the void evolution mechanism and to suit the model for 3D simulations. This task demands special numerical methods beyond FEM, such as the boundary-integral method. Furthermore, in real face-centered-cubic metals like copper, surface diffusion is strongly anisotropic and its impact on the electromigration-driven morphological evolution of voids has important consequences. Voids form in grains with a preference for certain crystallographic orientations and open circuit failure occurs when the void changes its shape to become a slit running perpendicular to the length of the metal line. Furthermore, it has been shown that the choice of appropriate crystal orientation with respect to the applied electric field might increase the lifetime of metal interconnects. Therefore, future works should address the effect of anisotropy and its implications for the void evolution problems.