A.2.3.2 Dynamic CMOS Logic

The basic idea of dynamic logic is depicted in Fig. A.13(d): the output node (Y is precharged by a PMOS transistor during the LOW-phase of the clocking signal clk. When the clock goes LOW the output is discharged by the n-block or not, depending on its logic function $F({\bf x})$. Due to the parasitic and interconnect capacitances the output remains stable for some time also in the HIGH state. Unfortunately, cascading such dynamic gates would not work because, due to the precharging of the preceding stage, the inputs may be still HIGH at the rising edge of the clock, which results in an erroneous discharge of the following stage.

One way to circumvent this problem is to use the dual n-block and an inverting buffer at the output (see Fig. A.13(e)), which guarantees the inputs to be valid or LOW and thus allows arbitrary cascading. When the clock goes HIGH the first stage of the cascade discharges, i.e., its output goes HIGH, causing the following stage to discharge and so forth until the last stage has settled. Owing to the analogy this type is also called domino logic. As in the case of static CMOS the output buffer improves gate speed for large fan-out.

The big advantages of this type of logic is that the inputs are connected only to NMOS transistors so that the input load capacitance is much smaller. Therefore, dynamic logic is faster than static CMOS. Furthermore, for complex functions the transistor count is almost halved. The big disadvantages of this type of logic is the need for repeated charging and discharging even when the inputs do not change their state. Therefore, dynamic logic consumes more power than static CMOS despite the lower transistor count. Another problem is the sensitivity to leakage current of the n-block (in the order of ) when the output is HIGH (during the clock-HIGH phase). This imposes a lower limit to the clock frequency. Also, as the ratio $\ensuremath{I_{\mathit{off}}}\xspace /\ensuremath{I_{\mathit{on}}}\xspace$ is limited by the supply voltage (cf. Section A.2.1), must be above a certain limit (cf. Section 2.5), which also limits the power efficiency of dynamic logic.

These problems can be alleviated to some extent by using a positive feedback with a narrow PMOS transistor at the output buffer, which then works like a latch as shown in Fig. A.13(f). The extra charge needed to change the switch the latch causes a usually small speed penalty.