A monolithic integrated circuit contains not only the actual circuit components (as they are drawn in a circuit diagram), but also parasitics, interconnections, protection devices, and, in addition, devices which are required only because there is more than one device on the chip, i.e., isolation structures.
The main techniques to create the desired topography on the wafer are thermal oxidation of silicon, lithography, etching and deposition processes, conventional and selective epitaxial growth, viscous flow of deposited glasses (CVD oxides), formation of silicides, and chemical-mechanical polishing. The main techniques to create the desired dopant profiles are ion implantation and in-situ doping for dopant introduction, and thermal annealing to make the dopants electrically active. In some cases profiles are intentionally broadened with a diffusion process.
Single process steps are combined to a complete process flow with a few hundred steps for a typical CMOS process. Since any structure on the chip depends on most process steps there is a strong interdependence between the various steps and some particular advantage achieved with a clever change in the flow can cost dearly somewhere else (much like in a chess game).