Despite the recent reductions of standard supply voltage there is still ample room left at the bottom for further improvement, especially, in the case of portable electronics. Some severe problems anticipated because of the high leakage currents like, e.g., circuit malfunction due to degradation of the noise margins, turned out to be much less severe, at least, for circuits in static logic. An open issue still to be investigated remains the question which kind of logic style or circuit technique can replace conventional dynamic logic, probably, in combination with other circuit types.
Despite the still existing differences between the main stream CMOS technologies and Ultra-Low-Power CMOS the gap is closing up. More even, the SIA roadmap of 1997 [4] has brought a revision of the projections in the roadmap issue of 1994 [3] to more aggressive values, primarily regarding oxide thickness and leakage currents. To the same extent to which industry commits itself to target these aggressive numbers the technological infrastructure to implement true ULP technologies on a larger scale improves. Similarly, as the research in the field of Ultra-Low-Power technologies continues, many problems which main stream CMOS still has with lower voltages and higher leakage currents come closer to a solution.