Nowadays, it is common to use the simulation of semiconductor manufacturing processes as a mean to support the development of new products or processes. The aim of this technique is to rationalize these processes and, consequently the products, before they actually enter the production line, since experimental optimization is very expensive. Simulation of manufacturing processes helps to find the best possible configuration of the production process even if the production equipment can not be used yet. Extension or reconfiguration of the existing processes can be tested and evaluated before investment takes place.
Deposition and etching are two of the most important semiconductor manufacturing processes. The common aspect regarding the simulation of the deposition and etching processes is tracking moving boundaries. Roughly speaking, there are three categories of algorithms for surface evolution. The first one is the string-based method, the second one is the cell-based method, and finally the most recent is the level set method. This method avoids many problems inherent in the first two methods.
This work focuses on the development and implementation of a general purpose topography simulator in two and three dimensions using the level set method. Sophisticated algorithms and techniques such as narrow banding and fast marching methods for implementation of an efficient and fast simulator have been used. The simulator is capable of handling different physical models for deposition and etching. These models can be implemented in a completely separated module in the simulator. The parameters of different models are calibrated and optimized using measurements based on inverse modeling.
The great part of applications presented in this work was requested or inspired by our industrial partners. The applications regarding the design of interconnect lines were needed by Cypress Semiconductor Corporation (San Jose, CA, USA). The profiles of deposited layers and voids in two and three dimensions are simulated. The two-dimensional simulations predict the capacitances formed between the different metal layers that significantly determine the timing delays. In addition, three-dimensional void characteristics are simulated for gaining insight into possible layout design rules for avoiding cracking effects.
A predictive simulation of the deposition of silicon dioxide into trenches with different aspect ratios is performed for power MOSFETs from Infineon Technologies (Villach, Austria).
Finally, plasma etching for obtaining the etching profiles with minimum corner rounding is simulated for Toshiba R&D Center (Kawasaki, Tokyo).