Bibliography

  1. International Technology Roadmap for Semiconductors (ITRS), 2011.

  2. A. Acovic, G. L. Rosa, and Y. Sun, "A review of hot carrier degradation mechanism in MOSFETs," Microel. Reliab., vol. 36, no. 7/8, pp. 845-869, 1996.

  3. T. Ning, P. Cook, R. Dennard, C. Osburn, S. Schuster, and H. Yu, "1um most VLSI technology - part IV: hot-electron design constraints," IEEE Trans. Electron Dev., vol. 26, pp. 346-353, 1979.

  4. E. Takeda, "Hot-carrier effects in submicrometer MOS VLSIs," IEEE Proc., vol. 131, no. 5, pp. 153-162, 1984.

  5. C. Hu, S. Tam, F. Hsu, P.-K. Ko, T.-Y. Chan, and K. Terrill, "Hot-electron-induced MOSFET degradation model, monitor and improvement," IEEE Trans. Electron Dev., vol. 48, no. 4, pp. 375-385, 1985.

  6. P. Heremans, P. Bellens, G. Groeseneken, and H. Maes, "Consistent model for the hot carrier degradation in n-channel and p-channel MOSFETs," IEEE Trans. Electron Dev., vol. 35, no. 12, pp. 2194-2209, 1988.

  7. C. Hu, "Lucky electron model for channel hot electron emission," in Proc. International Electron Devices Meeting (IEDM), pp. 22-25, 1979.

  8. S. Rauch, F. Guarin, and G. La Rosa, "Impact of e-e scattering to the hot carrier degradation of deep submicron nMOSFETs," IEEE Electron Dev. Lett., vol. 19, no. 12, pp. 463-465, 1998.

  9. E. Takeda and N. Suzuki, "An empirical model for device degradation due to hot-carrier injection," IEEE Electron Dev. Lett., vol. 4, no. 5, pp. 111-113, 1983.

  10. J.-S. Goo, Y.-G. Kim, H. Lee, H.-Y. Kwon, and H. Shin, "An analytical model for hot-carrier-induced degradation of deep-submicron n-channel LDD MOSFETs," Solid-State Electron., vol. 38, no. 6, pp. 1191-1196, 1995.

  11. R. Dreesen, K. Croes, J. Manca, W. D. Ceunick, L. D. Schepper, A. Pergoot, and G. Groeseneken, "Modeling hot-carrier degradation of LDD nMOSFETs by using a high resolution measurement technique," Microel. Reliab., vol. 39, pp. 785-790, 1999.

  12. R. Dreesen, K. Croes, J. Manca, W. D. Ceunick, L. D. Schepper, A. Pergoot, and G. Groeseneken, "A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation," Microel. Reliab., vol. 41, pp. 437-443, 2001.

  13. R. Woltjer and G. Paulzen, "Universal description of hot-carrier-induced interface states in nMOSFETs," in Proc. International Electron Devices Meeting (IEDM), pp. 535-538, 1992.

  14. R. Woltjer, G. Paulzen, H. Pomp, H. Lifka, and P. Woerlee, "Three hot-carrier degradation mechanisms," IEEE Trans. Electron Dev., vol. 42, no. 1, pp. 109-115, 1995.

  15. K. Mistry and B. Doyle, "A model for AC hot-carrier degradation in n-channel MOSFET's," IEEE Electron Dev. Lett., vol. 12, no. 9, pp. 492-494, 1991.

  16. K. Mistry and B. Doyle, "AC versus DC hot-carrier degradation in n-channel MOSFET's," IEEE Trans. Electron Dev., vol. 40, no. 1, pp. 96-104, 1993.

  17. S. Rauch, G. La Rosa, and F. Guarin, "Role of e-e scattering in the enhancement of channel hot carrier degradation of deep-submicron nMOSFETs at high Vgs conditions," IEEE Trans Dev. Material. Reliab., vol. 1, no. 2, pp. 113-119, 2001.

  18. C. Guerin, V. Huard, and A. Bravaix, "The energy-driven hot-carrier degradation modes of nMOSFETs," IEEE Trans. Dev. Material. Reliab., vol. 7, no. 2, pp. 225-235, 2007.

  19. P. Moens and G. van den Bosch, "Characterization of total self-operating area of lateral DMOS transistors," IEEE Trans. Electron Dev., vol. 6, no. 3, pp. 349-357, 2006.

  20. P. Moens, G. van den Bosch, and G. Groeseneken, "Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors," in Proc. International Reliability Physics Symposium (IRPS), pp. 214-221, 2003.

  21. P. Moens and M. Tack, "Hole trapping and de-trapping effects in LDMOS devices under dynamic stress," in Proc. International Electron Devices Meeting (IEDM), 2006.

  22. P. Moens, F. Bauwens, M. Nelson, and M. Tack, "Electron trapping and interface trap generation in drain extended pMOS transistors," in Proc. International Reliability Physics Symposium (IRPS), pp. 93-96, 2005.

  23. W. McMahon, A. Haggaag, and K. Hess, "Reliability scaling issues for nanoscale devices," IEEE Trans. Nanotech., vol. 2, no. 1, pp. 33-38, 2003.

  24. K. Hess, A. Haggag, W. McMahon, K. Cheng, J. Lee, and J. Lyding, "The physics of determining chip reliability," Circuits and Devices Mag., pp. 33-38, 2001.

  25. O. Penzin, A. Haggag, W. McMahon, E. Lyumkis, and K. Hess, "MOSFET degradation kinetics and its simulation," IEEE Trans. Electron Dev., vol. 50, no. 6, pp. 1445-1450, 2003.

  26. H. Kufluoglu and M. Alam, "A computational model of NBTI and hot carrier injection time-exponents for MOSFET reliability," Journ. Comput. Electron., vol. 3, pp. 165-169, 2004.

  27. H. Kufluoglu, MOSFET degradation due to negative bias temperature instability (NBTI) and hot carrier degradation (HCI) and its applications for reliability-aware VLSI design. PhD thesis, Purdue University, West Lafayette, Indiana, USA, 2007.

  28. S. Rauch and G. L. Rosa, "The energy driven paradigm of nMOSFET hot carrier effects," in Proc. International Reliability Physics Symposium (IRPS), 2005.

  29. S. Rauch and G. L. Rosa, "CMOS hot carrier: From physics to end of life projections, and qualification," in Proc. International Reliability Physics Symposium (IRPS), tutorial, 2010.

  30. A. Bravaix, C. Guerin, V. Huard, D. Roy, J. Roux, and E. Vincent, "Hot-carrier acceleration factors for low power management in DC-AC stressed 40nm nMOS node at high temperature," in Proc. International Reliability Physics Symposium (IRPS), pp. 531-546, 2009.

  31. C. Guerin, V. Huard, and A. Bravaix, "General framework about defect creation at the Si/SiO2 interface," Journ. Appl. Phys., vol. 105, no. 114513, 2009.

  32. W. McMahon, K. Matsuda, J. Lee, K. Hess, and J. Lyding, "The effects of a multiple carrier model of interface states generation of lifetime extraction for MOSFETs," in Proc. Int. Conf. Mod. Sim. Micro, vol. 1, pp. 576-579, 2002.

  33. K. Hess, I. C. Kizilyalli, and J. W. Lyding, "Giant isotope effect in hot electron degradation of metal oxide silicon devices," IEEE Trans Electron Dev., vol. 45, no. 2, pp. 406-416, 1998.

  34. T. Grasser, W. Gös, and B. Kaczer, "Critical modeling issues in negative bias temperature instability," ECS Transactions, vol. 19, no. 2, pp. 265-287, 2009.

  35. W. Chang, B. Davari, M. Wordeman, Y. Taur, C. Hsu, and M. Rodriguez, "A high performance 0.25um CMOS technology. I. design and characterization," IEEE Trans. Electron Dev., vol. 39, p. 959, 1992.

  36. D. Bursky, "ASIC family crams up to 1.2mum usable gates/chip," Electronic Design, vol. 41, pp. 111-116, 1993.

  37. D. Frank, R. Dennard, E. Nowak, P. Solomon, M. Stettler, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Proc. VLSI Symposium Tech. Digest, pp. 174-175, 2000.

  38. L. Hong, Characterization of hot carrier reliability in deep submicrometer MOSFETs. PhD thesis, National University of Singapore, 2005.

  39. F.-C. Hsu and K.-Y. Chu, "Evaluation of LDD MOSFET's based on hot-electron-induced degradation," IEEE Electron Dev. Lett., vol. 5, no. 5, pp. 162-165, 1984.

  40. A. Haggag, W. McMahon, K. Hess, K. Cheng, J. Lee, and J. Lyding, "High-performance chip reliability from short-time-tests. statistical models for optical interconnect and HCI/TDDB/NBTI deep-submicron transistor failures," in Proc. International Reliability Physics Symposium (IRPS), pp. 271-279, 2001.

  41. A. Bravaix and V. Huard, "Hot-carrier degradation issues in advanced CMOS nodes," in Proc. European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF), tutorial, 2010.

  42. T. Mizuno, A. Toriumi, M. Iwase, M. Takanashi, H. Niiyama, M. Fukmoto, and M. Yoshimi, "Hot-carrier effects in 0.1 um gate length CMOS devices," in Proc. International Electron Devices Meeting (IEDM), pp. 695-698, 1992.

  43. J. Bude, "Gate-current by impact ionization feedback in submicron MOSFET technologies," in Proc. VLSI Symposium Tech. Digest, pp. 101-102, 1995.

  44. F. Venturi, E. Sangiorgi, and B. Ricco, "The impact of voltage scaling on electron heating and device performance of submicrometer MOSFET's," IEEE Trans. Electron Dev., vol. 38, no. 8, pp. 1895-1904, 1991.

  45. J. Chung, M. Jeng, J. Moon, P. Ko, and C. Hu, "Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFET's," IEEE Trans. Electron Dev., vol. 37, pp. 1651-1657, 1990.

  46. M. Fischetti and S. Laux, "Monte-Carlo study of sub-band-gap impact ionization in small silicon field-effect transistors," in Proc. International Electron Devices Meeting (IEDM), pp. 305-308, 1995.

  47. D. Brisbin, P. Lindorfer, and P. Chaparala, "Substrate current independent hot carrier degradation in nLDMOS devices," in Proc. International Reliability Physics Symposium (IRPS), pp. 329-333, 2006.

  48. M. Annese, S. Carniello, and S.Manzini, "Design and optimization of a hot-carrier resistant high-voltage nMOS transistor," IEEE Trans. Electron Dev., vol. 52, no. 7, pp. 1634-1639, 2005.

  49. P. Santos, H. Quaresma, A. Silva, and M. Lanca, "High-voltage nMOS design in fully implanted twin-well CMOS," Microel. Jour., vol. 35, no. 9, pp. 723-730, 2004.

  50. W. Qin, W. Chim, D. H. Chan, and C. Lou, "Modelling the degradation in the subthreshold characteristics of submicrometre LDD pMOSFETs under hot-carrier stressing," Semicond. Sci. Technol., vol. 13, no. 5, pp. 453-459, 1998.

  51. S. Manzini and A. Gallerano, "Avalanche injection of hot holes in the gate oxide of LDMOS," Solid-State Electron., vol. 44, no. 1, pp. 1325-1330, 2000.

  52. V. Reddy, "An introduction to CMOS semiconductor reliability," in Proc. International Reliability Physics Symposium (IRPS), tutorial, 2004.

  53. P. Moens, G. van den Bosch, C. D. Keukeleire, R. Degraeve, M. Tack, and G. Groseneken, "Hot hole degradation effects in lateral nDMOS transistors," IEEE Trans. Electron Dev., vol. 51, no. 10, pp. 1704-1710, 2004.

  54. D. Brisbin, A. Strachan, and P. Chaparala, "3-d and 2-d hot carrier layout optimization of n-LDMOS transistor arrays," in Proc. International Integrated Reliability Workshop (IIRW), pp. 120-124, 2002.

  55. S. Manzini and C. Contiero, "Hot-electron-induced degradation in high-voltage submicron DMOS transistors," in Proc. International Symposium on Power semiconductor Devices and IC's, pp. 65-68, 1996.

  56. Q. Wang, L. Sun, and A. Yap, "Investigation of hot carrier degradation in asymmetric nDEMOS transistors," Microel. Reliab., vol. 48, pp. 508-513, 2008.

  57. Q. Wang, L. Sun, Z. Zhang, A. Yap, H. Li, and S. Liu, "Locating hot carrier degradation in asymmetric nDEMOS transistors by gated diode technique," Journ. Non-Crystalline Solids, vol. 354, pp. 1871-1875, 2008.

  58. K.-M. Wu, J. Chen, Y. Su, J. Lee, K. Lin, J. Shih, and S. Hsu, "Effects of gate bias on hot-carrier reliability in drain extended metal-oxide-semiconductor transistors," Appl. Phys. Lett., vol. 89, no. 183522, 2006.

  59. J. Lee, J. Chen, K.-M. Wu, C. Liu, and S. Hsu, "Effect of hot-carrier-induced interface states distribution on linear drain current degradation in 0.35um n-type lateral diffused metal-oxide-semiconductor transistors," Appl. Phys. Lett., vol. 92, no. 103510, 2008.

  60. J. Chen, S.-Y. Chen, K.-M. Wu, and C. Liu, "Investigation of hot-carrier-induced degradation mechanisms in p-type high-voltage drain extended metal-oxide-semiconductor transistors," Jpn. Journ. Appl. Phys., vol. 48, no. 04C039, 2009.

  61. J. Chen, S.-Y. Chen, K.-M. Wu, and C. Liu, "Channel length dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor transistors," Appl. Phys. Lett., vol. 93, no. 223504, 2008.

  62. J. Chen, K.-S. Tian, S.-Y. Chen, K.-M. Wu, and C. Liu, "Mechanism and modeling of on-resistance degradation in n-type lateral diffused metal-oxide-semiconductor transistors," Jpn. Journ. Appl. Phys., vol. 48, no. 04C040, 2009.

  63. M. Pagey, "Characterization and modeling of hot-carrier degradation in sub-micron nMOSFETs," Master's thesis, Vanderbilt University, Aug. 2002.

  64. International Technology Roadmap for Semiconductors (ITRS), 2009.

  65. M. Ancona, N. Saks, and D. McCarthy, "Lateral disrtribution of hot-carrier-induced interface traps in MOSFET's," IEEE Trans Electron Dev., vol. 35, no. 12, pp. 221-2228, 1988.

  66. S. Mahapatra, C. Parikh, V. Rao, C. Viswanathan, and J. Vasi, "Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFET's," IEEE Trans. Electron Dev., vol. 47, no. 4, pp. 789-796, 2000.

  67. S. Cristoloveanu, H. Haddara, and N. Revil, "Defect localization induced by hot carrier injection in short-channel MOSFETs: concept, modeling and characterization," Microel. Reliab., vol. 33, no. 9, pp. 1365-1385, 1993.

  68. F.-C. Hsu and K.-Y. Chu, "Temperature dependence of hot-electron induced degradation in MOSFET's," IEEE Electron Dev. Lett., vol. 5, no. 5, pp. 148-150, 1984.

  69. P. Heremans, G. V. den Bosch, R. Bellens, G. Groseneken, and H. Maes, "Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's," IEEE Trans. Electron Dev., vol. 37, no. 4, pp. 980-992, 1990.

  70. M. Song, K. MacWilliams, and C. Woo, "Comparison of nMOS and pMOS hot carrier effects from 300 to 77 K," IEEE Trans. Electron Dev., vol. 44, no. 2, pp. 268-276, 1997.

  71. A. Bravaix, D. Goguenheim, N. Revil, E. Vincent, M. Varrot, and P. Mortini, "Analysis of high temperatures effects on performance and hot-carrier degradation in DC/AC stressed 0.35 um n-MOSFETs," Microel. Reliab., vol. 39, no. 1, pp. 35-44, 1999.

  72. P. Moens, J. Mertens, F. Bauwens, P. Joris, W. D. Ceuninck, and M. Tack, "A comprehensive model for hot carrier degradation in LDMOS transistors," in Proc. International Reliability Physics Symposium (IRPS), pp. 492-497, 2007.

  73. H. Enichlmair, S. Carniello, J. Park, and R. Minixhofer, "Analysis of hot carrier effects in a 0.35 um high voltage n-channel LDMOS," Microel. Reliab., vol. 47, no. 9-11, pp. 1439-1443, 2007.

  74. K. Lee, C. Kang, O. S. Yoo, R. Choi, B. Lee, J. Lee, H.-D. Lee, and Y.-H. Jeong, "PBTI-associated high-temperature hot carrier degradation of nMOSFETs with metal-gate/high-k dielectrics," IEEE Electron Dev. Lett., vol. 29, pp. 389-391, Apr. 2008.

  75. M. Jo, S. Kim, C. Cho, M. Chang, and H. Hwang, "Gate voltage dependence on hot carrier degradation at an elevated temperature in a device with ultrathin silicon oxynitride," Appl. Phys. Lett., vol. 94, no. 5, pp. 053505-1-053505-3, 2009.

  76. E. Amat, T. Kauerauf, R. Degraeve, R. Rodriguez, M. Nafria, X. Aymerich, and G. Groeseneken, "Channel hot-carrier degradtion in pMOS and nMOS short channel transistors with high-k dielectric stack," Microel. Engineering, vol. 87, no. 1, pp. 47-50, 2010.

  77. A. Ludikhuize, "Kirk effect limitations of HV IC's," in Proc. International Symposium on Power Semiconductor devices and IC's, pp. 249-252, 1994.

  78. A. Ludikhuize, M. Slotboom, A. Nezar, N. Nowlin, and R. Brock, "Analysis of hot-carrier-induced degradation and snapback in submicron 50V lateral MOS transistors," in Proc. International Symposium on Power Semiconductor devices and IC's, pp. 53-56, 1997.

  79. K.-M. Wu, Development and hot-carrier reliability study of integrated high-voltage MOSFET transistor. PhD thesis, National Cheng Kung University Tainan, 2007.

  80. H. Wu, W. Sun, Y. Yi, H. Li, and L. Shi, "The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide," Microel. Reliab., vol. 48, no. 11-12, pp. 1804-1808, 2008.

  81. C. Gao, J. Wang, L. Wang, A. Yap, and H. Li, "Two-stage hot-carrier degradation behavior of 0.18 um 18V n-type DEMOS and its recovery effect," Microel. Reliab., vol. 49, no. 1, pp. 8-12, 2009.

  82. B. Doyle, M. Bourcerie, J.-C. Marchetaux, and A. Boudou, "Relaxation effects in nMOS transistors after hot-carrier stressing," IEEE Electron Dev. Lett., vol. 8, no. 5, pp. 234-236, 1987.

  83. P. Cuevas, "A simple explanation for the apparent relaxation effect associated with hot-carrier phenomenon in MOSFET's," IEEE Electron Dev. Lett., vol. 9, no. 12, pp. 627-629, 1988.

  84. C. Young, J. Yang, K. Metthews, S. Suthram, M. Hussain, G. Bersuker, C. Smith, R. Harris, R. Choi, B. Lee, and H.-H. Tseng, "Hot carrier degradation in HfSiON/TiN fin shaped field effect transistor with different substrate orientation," J. Vac. Sci. Technol. B, vol. 27, no. 1, pp. 468-471, 2009.

  85. S.-Y. Chen, C.-H. Tu, J.-C. Lin, M.-C. Wang, P.-W. Kao, M.-H. Ling, S.-H. Wu, Z.-W. Jhou, J. Ko, and H.-S. Haung, "Investigation of DC hot-carrier degradation at elevated temperatures fro p-channel metal-oxide-semiconductor field-effect transistors of 0.13 um technology," Jpn. Journ. Appl. Phys., vol. 47, pp. 1527-1531, 2008.

  86. H. Enichlmair, J. Park, S. Carniello, B. Loeffer, R. Minixhofer, and M. Levy, "Hot carrier straess degradation modes in p-type high voltage LDMOS transistors," in Proc. International Reliability Physics Symposium (IRPS), pp. 426-430, 2009.

  87. C. Salm, A. Hof, F. Kuper, and J. Schmitz, "Reduced temperature dependence of hot carrier degradation in deuterated nMOSFETs," Microel. Reliab., vol. 46, no. 9-11, pp. 1617-1622, 2006.

  88. Z. Chen, P. Ong, A. Mylin, V. Singh, and S. Cheltur, "Direct evidence of multiple vibrational excitation for the Si-H/D bond breaking in metal-oxide-semiconductor transistors," Appl. Phys. Lett., vol. 81, no. 17, pp. 3278-3280, 2002.

  89. E. Li, E. Rosenbaum, J. Tao, G.-F. Yeap, M. Lin, and P. Fang, "Hot-carrier effects in nMOSFETs in 0.1 um CMOS technology," in Proc. International Reliability Physics Symposium (IRPS), pp. 253-258, 1999.

  90. C. Lin, S. Biesemans, L. Han, K. Houlihan, T. Schiml, K. Schruefer, C. Wann, and R. Markhopf, "Hot carrier reliability for 0.13 um CMOS technology with dual gate oxide thickness," in Proc. International Electron Devices Meeting (IEDM), pp. 135-138, 2000.

  91. R. Woltjer, A. Hamada, and E. Takeda, "pMOSFET hot carrier damage: oxide charge and interface states," Semicond Sci. Technol., vol. 7, pp. pp. B581-B584, 1992.

  92. A. Bravaix, D. Goguenheim, N. Revil, and E. Vincent, "Hole injection enhanced hot-carrier degradation in pMOSFETs used for systems on chip applications with 6.5-2nm thick gate oxides," Microel. Reliab., vol. 44, no. 1, pp. 65-77, 2004.

  93. T. Grasser, H. Kosina, and S. Selberherr, "Influence of the distribution function shape and the band structure on impact ionization modeling," Journ. Appl. Phys., vol. 90, no. 12, pp. 6165-6171, 2001.

  94. A. Gehring, T. Grasser, H. Kosina, and S. Selberherr, "Simulation of hot-electron oxide tunneling current based on a non-Maxwellian electron energy distribution function," Journ. Appl. Phys., vol. 92, no. 10, pp. 6019-6027, 2002.

  95. T. Grasser, H. Kosina, and S. Selberherr, "Hot carrier effects within macroscopic transport models," International Journal of High Speed Electronics and Systems, vol. 13, no. 3, pp. 873-901, 2003.

  96. A. Zaka, Q. Rafhay, M. Iellina, P. Palestri, R. Clerc, D. Rideau, D. Garetto, J. Singer, G. Pananakakis, C. Tavernier, and H. Jaouen, "On the accuracy of current TCAD hot carrier injection models in nanoscale devices," Solid-State Electron., vol. 54, pp. 1669-1674, 2010.

  97. M. Vasicek, J. Cervenka, D. Esseni, P. Palestri, T. Grasser, "Applicability of macroscopic transport models to decananometer MOSFETs," IEEE Trans. Electron Dev., vol. 59, pp. 639 - 646, 2012.

  98. B. Persson and P. Avouris, "Local bond breaking via STM-induced excitations: the role of temperature," Surface Science, vol. 390, pp. 45-54, 1997.

  99. K. Hess, L. Register, B. Tuttle, J. Lyding, and I. Kizilyalli, "Impact of nanostructure research on conventional solid-state electronics: the giant isotope effect in hydrogen desorption and CMOS lifetime," Physica E, vol. 3, pp. 1-7, 1998.

  100. D. Wolters and A. Z.-V. Duyhoven, "Trapping of hot electrons," Appl. Surf. Sci, vol. 39, pp. 565-577, 1989.

  101. R. Woltjer and G. Paulzen, "Modeling of oxide-charge generation during hot-carrier degradation of pMOSFET's," IEEE Trans. Electron Dev., vol. 41, no. 9, pp. 1639-1645, 1994.

  102. S. Mahapatra, D. Parikh, V. Rao, C. Viswanathan, and J. Vasi, "A comprehensive study of hot-carrier induced interface and oxide trap distribution in MOSFET's using a novel charge pumping technique," IEEE Trans. Electron Dev., vol. 47, no. 1, pp. 171-177, 2000.

  103. S. Samanta, N. Patel, K. ManjulaRani, and K. Jang, "Stress voltage dependence HCI induced traps distribution in 60V nLDMOS," IIRW Final Report, pp. 120-123, 2009.

  104. C. Cheng, K. Tu, T. Wang, T. Hsieh, J. Tzeng, Y. Yong, R. Liou, and S. Hsu, "Investigation of hot carrier degradation modes in LDMOS by using a novel three-region charge pumping technique," in Proc. International Reliability Physics Symposium (IRPS), pp. 334-337, 2006.

  105. D. Fleetwood, "Fast and slow border traps in MOS devices," IEEE Trans. Nuclear Sci., vol. 43, no. 3, pp. 779-786, 1996.

  106. D. Fleetwood, H. Xiong, Z.-Y. Lu, J. Felix, R. Schrimpf, and S. Pantelidis, "Unified model of hole trapping, 1/f noise, and thermally activated current in MOS devices," IEEE Trans. Nuclear Sci., vol. 49, no. 6, pp. 2674-2683, 2002.

  107. A. Bravaix, C. Trapes, N. Revil, and E. Vincent, "Carrier injection efficiency for the reliability study of 3.5-1.2 nm thick gate-oxide CMOS technologies," Microel. Reliab., vol. 43, no. 8, pp. 1241-1246, 2003.

  108. A. Schwerin, W. Hänsch, and W. Weber, "The relationsjip between the oxide charge and device degradation: a comparative study of n- and p-channel MOSFET's," IEEE Trans. Electron Dev., vol. 34, no. 12, pp. 2493-2500, 1987.

  109. D. DiMaria and J. Stasiak, "Trap creation in silicon dioxide produced by hot electrons," Journ. Appl. Phys., vol. 65, no. 6, pp. 2342-2356, 1989.

  110. D. DiMaria, "Defect generation under substrate-hot-electron injection into ultrathin silicon dioxide layers," Journ. Appl. Phys., vol. 86, no. 4, pp. 2100-2109, 1999.

  111. H. Momose, S.-I. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, "A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime," IEDM Technical Digest, pp. 453-456, 1997.

  112. I. Polishchuk, Y.-C. Yeo, Q. Lu, T.-J. King, and C. Hu, "Hot-carrier reliability of p-MOSFET with ultra-thin silicon nitride gate dielectric," in Proc. International Reliability Physics Symposium (IRPS), pp. 425-430, 2001.

  113. J. Sim, B. Lee, R. Choi, K. Matthews, D. Kwong, L. Larson, P. Tsui, and G. Bersuker, "Hot carrier reliability of HfSiON nMOSFETs with poly and TiN metal gate," Device Research Conference, vol. 1, pp. 99-100, 2004.

  114. J. Sim, B. Lee, R. Choi, S.-C. Song, and G. Bersuker, "Hot carrier degradation of HfSiON gate dielectrics with TiN electrode," IEEE Trans. Dev. Material Realiab., vol. 5m, no. 2, pp. 117-182, 2005.

  115. N. Chowdhurz, P. Srinivasan, and D. Misra, "Trapping in deep defects under substrate hot electron stress in TiN/Hf-silicate based gate stacks," Solid-State Electron., vol. 51, pp. 102-110, 2007.

  116. A. Sarwar, M. Siddiqui, R. Siddiqui, and Q. Khosru, "Effects of interface traps and oxide traps on gate capacitance of MOS devices with ultrathin (EOT~1 nm) high-k stacked gate devices," TENCON, pp. 1-5, 2009.

  117. S.-G. Hu, Y. Hao, X.-H. Ma, Y.-R. Cao, C. Chen, and X.-F. Wu, "Hot-carrier stress effects on GIDL and SILC in 90 nm LDD-MOSFET with ulgtra-thin gate oxide," Chin. Phys. Lett., vol. 26, no. 1, 2009.

  118. E. Nicollian, C. Berglund, P. Schmidt, and J. Andrews, "Electrochemical charging of thermal SiO2 films by injected electron currents," Journ. Appl. Phys., vol. 42, no. 12, pp. 5654-5664, 1971.

  119. T. Ning, "Thermal reemission of trapped electrons in SiO2," Journ. Appl. Phys., vol. 49, no. 12, pp. 5997-6003, 1978.

  120. D. Young, E. Irene, D. DiMaria, R. D. Keersmaecker, and H. Massoud, "Electron trapping in SiO2 at 295 and 77 K," Journ. Appl. Phys., vol. 50, no. 10, pp. 6366-6372, 1979.

  121. D. Wolters and J. van der Schoot, "Kinetics of charge trapping in dielectrics," Journ. Appl. Phys., vol. 58, no. 2, pp. 831-837, 1985.

  122. J. Maserjian and N. Zamani, "Observation of positively charged state generation near the Si/SiO2 interface during Fowler-Nordheim tunneling," Journ. Vacuum Sci. Technol., vol. 20, no. 3, pp. 743-746, 1982.

  123. R. Rofam and C. Hu, "Stress-induced oxide leakage," IEEE Electron Dev. Lett., vol. 12, no. 11, pp. 632-634, 1991.

  124. T. Wang, N.-K. Zous, J.-L. Lai, and C. Huang, "Hot hole stress induced leakage current (SILC) transient in tunnel oxides," IEEE Electron Dev. Lett., vol. 19, no. 11, pp. 411-413, 1998.

  125. D. Dumin and J. Maddux, "Correlation of stress-induced leakage current in thin oxides with trap creation inside the oxides," IEEE Trans. Electron Dev., vol. 90, no. 5, pp. 986-992, 1993.

  126. S. Mahapatra, D. Saha, and P. Kumar, "On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress," IEEE Trans. Electron Dev., vol. 53, no. 7, pp. 1583-1592, 2006.

  127. S. Tsujikawa, "SILC and NBTI in pMOSFETs with ultrathin SiON gate dielecrtics," IEEE Trans. Electron Dev., vol. 54, no. 3, pp. 524-530, 2007.

  128. D. Schroder, "Negative bias temperature instability: what do we understand?," Microel. Reliab., vol. 47, no. 6, pp. 841-852, 2007.

  129. Y.-R. Cao, Y. Hao, X.-H. Ma, L. Yu, and S.-G. Hu, "SILC during NBTI stress in pMOSFETs with ultra-thin SiON gate dielectric," Chin. Phys. Lett., vol. 25, no. 4, pp. 1427-1430, 2008.

  130. A. Schenk and U. Krumbein, "Coupled defect-level recombination: Theory and application to anomalous diode characteristics," Journ. Appl. Phys., vol. 78, no. 5, pp. 3185-3191, 1995.

  131. P. Bloechl, "First-principle calculations of defects in oxygen-deficient silica exposed to hydrogen," Phys. Rev. B, vol. 62, no. 10, pp. 6159-6179, 2000.

  132. M. Houssa, A. Stesmans, and M. Heyns, "Model for the trap-assistant tunneling current through very thin SiO2/ZrO2 gate dielectric stacks," Semicond. Sci. Technol., vol. 16, pp. 427-432, 2001.

  133. L. Larcher, "Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model," IEEE Trans. Electon Dev., vol. 50, no. 2, pp. 1246-1253, 2003.

  134. O. Blank, H. Reisinger, R. Stengl, M. Gutsche, F. Weist, V. Capodieci, J. Schulze, and I. Eisele, "A model for multistep trap-assisted tunneling in thin high-k dielectrics," Journ. Appl. Phys., vol. 97, no. 4, 2005.

  135. G. Bersuker, D. Heh, C. Young, H. Park, P. Khanal, L. Larcher, A. Padovani, P. Lenahan, J. Ryan, B. Lee, H. Tseng, and R. Jammy, "Breakdown in the metal/high-k gate stack: identifying the "weak link" in the multilayer dielectric," IEDM Technical Digest, pp. 791-794, 2008.

  136. T. Grasser, H. Reisinger, P.-J. Wagner, D. Kaczer, F. Schanowsky, and W. Gös, "The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability," in Proc. International Reliability Physics Symposium (IRPS), pp. 16-25, 2010.

  137. T. Aichinger, M. Nelhiebel, and T. Grasser, "On the temperature dependence of NBTI recovery," Microel. Reliab., vol. 48, pp. 1178-1184, 2008.

  138. T. Grasser, B. Kaczer, W. Goes, H. Reisinger, T. Aichinger, P. Hehenberger, P.-J. Wagner, F. Schanowsky, J. Franco, P. Roussel, and M. Nelhiebel, "Recent advances in understanding the bias temperature instability," in Proc. International Electron Devices Meeting (IEDM), pp. 82-85, 2010.

  139. R. Walkup, D. Newns, and P. Avouris, "Role of mutliple inelastic transistions in atom transfet with the scanning tunneling microscope," Phys. Rev. B, vol. 48, no. 3, pp. 1858-1861, 1993.

  140. J. Lyding, K. Hess, G. Abeln, D. Thompson, J. Moore, M. Hersam, E. Foley, J. Lee, S. Hwang, H. Choi, P. Avouris, and I. Kizialli, "Ultrahigh vacuum-scanning tunneling microscopy nanofabrication and hydrogen/deuterium desorption from silicon surfaces: implications for complementary metal oxide semiconductor technology," Appl. Surf. Sci., vol. 13-132, pp. 221-230, 1998.

  141. K. Stokbro, C. Thirstrup, M. Sakurai, U. Quaade, B. Y.-K. Hu, F. Perez-Murano, and F. Grey, "STM-induced hydrogen desorption via a hole resonance," Phys. Rev. Lett., vol. 80, pp. 2618-2621, 1998.

  142. M. Budde, G. Lüpke, E. Chen, X. Zhang, N. H. Tolk, L. C. Feldman, E. Tarhan, A. K. Ramdas, and M. Stavola, "Lifetimes of hydrogen and deuterium related vibrational modes in silicon," Phys. Rev. Lett., vol. 87, no. 4, pp. 1455-1461, 2001.

  143. J. Sune and Y. Wu, "Hydrogen-release mechanisms in the breakdown of thin SiO2 films," Phys. Rev. Lett., vol. 92, no. 8, pp. 087601 (1-4), 2004.

  144. J. Sune and Y. Wu, "Mechanisms of hydrogen release in the breakdown of SiO2-based oxides," in Proc. International Electron Devices Meeting (IEDM), pp. 388-391, 2005.

  145. R. Biswas, Y.-P. Li, and B. C. Pan, "Enhanced stability of deuterium in silicon," Appl. Phys. Lett., vol. 72, no. 26, pp. 3500-3503, 1998.

  146. G. Ribes, S. Bruyere, M. Denais, F. Monsieur, V. Huard, D. Roy, and G. Ghibaudo, "Multi-vibrational hydrogen release: physical origin of Tbd,Qbd power-law voltage dependence of oxide breakdown in ultra-thin gate oxides," Microel. Reliab., vol. 45, pp. 1842-1854, 2005.

  147. B. Tuttle and C. V. de Walle, "Structure, energetics, and vibrational properties of Si-H bond dissociation in silicon," Phys. Rev. B, vol. 59, no. 20, pp. 12884-12889, 1999.

  148. K. Hess, A. Haggag, W. McMahon, B. Fischer, K. Cheng, J. Lee, and L. Lyding, "Simulation of Si-SiO2 defect generation in CMOS chips: From atomistic structure to chip failure rates," in Proc. International Electron Devices Meeting (IEDM), pp. 93-96, 2000.

  149. H. Kufluoglu and M. Alam, "A geometrical unification of the theories of NBTI and HCI time exponents and its implications for ultra-scaled planar and surround-gate MOSFETs," in Proc. International Electron Devices Meeting (IEDM), pp. 113-116, 2004.

  150. T.Grasser, W. Gös, and B. Kaczer, "Dispersive transport and negative bias temperature instability: boundary conditions, initial conditions, and transport models," IEEE Trans. Dev. Material. Reliab., vol. 8, no. 1, pp. 79-97, 2008.

  151. T. Grasser, H. Reisinger, W. Goes, T. Aichinger, P. Hehenberger, P.-J. Wagner, M. Nelhiebel, J. Franco, and B. Kaczer, "Switching oxide traps as the missing link between negative bias temperature instability and random telegraph noise," in Proc. International Electron Devices Meeting (IEDM), 2009.

  152. S. Rauch and G. L. R. and, "The energy-driven paradigm of nMOSFET hot-carrier effects," IEEE Trans. Dev. Material. Reliab., vol. 5, no. 4, pp. 701-705, 2005.

  153. C. Gardner, "The classical and quantum hydrodynamic models.," in Proc. Intl. Workshop on Computational Electronics, (University of Leeds), pp. 25-36, 1993.

  154. C. Jungemann and B. Meinerzhagen, Hierarchical Device Simulation. Springer Verlag Wien/New York, 2003.

  155. S. Sze and K. Ng, Physics of semiconductor devices. Wiley-Interscience publication, Wiley-Interscience, 2007.

  156. M.-T. Vasicek, Advanced macroscopic transport models. PhD thesis, Vienna Technical University, Vienna, Austria, 2009.

  157. Sentaurus device Monte Carlo user guide, SYNOPSYS, inc., 2009.

  158. S.-M. Hong and C. Jungemann, "A fully coupled scheme for a Boltzmann-Poisson equation solver based on a spherical harmonics expansion," Journ. Comput. Electron., vol. 8, no. 3-4, pp. 225-241, 2009.

  159. K. Rupp, Numerical solution of the Boltzmann transport equation, PhD thesis, Vienna Technical University, Vienna, Austria, 2012.

  160. K. Rupp, C. Jungemann, M. Bina, A. Jüngel, T. Grasser, "Bipolar spherical harmonics expansions of the Boltzmann transport equation," in Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD),pp. 19-22 2012.

  161. A. Gnudi, D. Ventura, G. Baccarani, and F. Oden, "Two-dimensional MOSFET simulations by means of of a multidimensional spherical harmonics expansion of the Boltzmann transport equation," Solid-State Electron., vol. 36, no. 4, pp. 575-581, 1993.

  162. S.-M. Hong, C. Jungemann, and M. Bollhofer, "A deterministic Bolzmann equation solver for two-dimensional semiconductor devices," in Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 293-296, 2008.

  163. Institute for Microelectronic, TU Wien, MiniMOS-NT Device and Circuit Simulator.

  164. W. Emden, W. Krautschneider, G. Tempel, R. Hagenbeck, and F. Beug, "A modified constant field charge pumping method for sensitive profiling of near-junction charges," in Proc. European Solid-State Device Research Conference (ESSDERC), pp. 279-282, 2007.

  165. H.-S. Wong, M. White, J. Krutsick, and R. Booth, "Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's," Solid-State Electron., vol. 30, no. 9, pp. 953-958, 1987.

  166. A. G. Prakash, S. Ke, and K. Siddappa, "High-energy radiation effects on subthreshold characteristics, transconductance and mobility of n-channel MOSFETs," Semicond. Sci. Technol., vol. 18, no. 12, pp. 1037-1042, 2003.

  167. J. Wang-Ratkovic, R. Lacoe, K. Williams, M. Song, S. Brown, and G. Yabiku, "New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures," in Proc. International Reliability Physics Symposium (IRPS), pp. 312-314, 2003.

  168. DESSIS ISE TCAD Manual Release 9.0, 2002.

  169. T. Grasser, C. Jungemann, H. Kosina, B. Meinerzhagen, and S. Selberherr, "Advanced transport models for sub-micrometer devices," in Proc. Simulation of Semiconductor Processes and Devices (SISPAD), pp. 1-8, 2004.

  170. A. Gehring, T. Grasser, H. Kosina, and S. Selberherr, "Simulation of hot-electron oxide tunneling current based on a non-Maxwellian electron energy distribution function," Journ. Appl. Phys., vol. 92, no. 10, pp. 6019-6027, 2002.

  171. C. Fiegna, F. Venturi, M. Melanotte, E. Sangiorgi, and B. Ricco, "Simple and efficient modeling of EPROM writing," IEEE Trans. Electron Dev., vol. 38, no. 3, pp. 603-610, 1991.

  172. G. Groeseneken, H. Maes, N. Beltran, and R.F. De Keersmaecker, "Reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Dev., vol. 31, pp. 42-53, 1984.

  173. P. Heremans, J. Witters, G. Groeseneken, and H. Maes, "Analysis of the charge pumping technique and its applicationfor the evaluation of the MOSFET degradation," IEEE Trans. Electron Dev., vol. 36, p. 1318, 1989.

  174. S. Okhonin, T. Hessler, and M. Dutoit, "Comparison of gate-induced drain leakage and charge pumping measurements for determining lateral interface trap profiles in electrically stressed MOSFET's," IEEE Trans. Electron Dev., vol. 43, no. 4, pp. 605-612, 1996.

  175. M. Tsuchiaki, H. Hara, T. Morimoto, and H. Iwai, "A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFET's," IEEE Trans Electron Dev., vol. 40, no. 10, pp. 1768-1799, 1993.

  176. S. Chung and J.-J. Yang, "A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's," IEEE Trans. Electron Dev., vol. 46, pp. 1371-1377, July 1999.

  177. W. K. Chim, S. E. Leang, and D. S. H. Chan, "Extraction of metal-oxide semiconductor field-effect-transistor interface state and trapped charge spatial distributions using a physics-based algorithm," Journ. Appl. Phys., vol. 81, no. 4, pp. 1992-1997, 1997.

  178. R. G.-H. Lee, J.-S. Su, and S. S. Chung, "A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's," IEEE Trans. Electron Dev., vol. 43, no. 1, pp. 81-89, 1996.

  179. H.-H. Li, Y.-L. Chu, and C.-Y. Wu, "A novel charge-pumping method for extracting the lateral distributions of interface-trap and effective oxide-trapped charge densities in MOSFET devices," IEEE Trans. Electron Dev., vol. 44, pp. 782-791, may 1997.

  180. A. Elliot and and, "The use of charge pumping currents to measure surface state densities in MOS transistors," Solid-State Electron., vol. 19, pp. 241-247, 1976.

  181. B. Djezzar, S. Oussalah, and A. Smatti, "A new oxide-trap based on charge-pumping (OTCP) extraction method for irradiated MOSFET devices: part I (high frequencies)," IEEE Trans. Nuclear Science, vol. 51, pp. 1724-1731, aug. 2004.

  182. H.-H. Li, Y.-L. Chu, and C.-Y. Wu, "A new simplified charge pumping current model and its model parameter extraction," IEEE Trans. Electron Dev., vol. 43, pp. 1857-1863, nov 1996.

  183. W. Chen, A. Q. Balasinski, and T. P. Ma, "Lateral profiling of oxide charge and interface traps near MOSFET junctions," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 187-196, 1993.

  184. N. Pesonen, W. Kahn, R. Allen, M. Cresswell, and M. Zaghloul, "Application of conformal mapping approximation techniques: parallel conductors of finite dimensions," IEEE Trans. Instrum. Meas., vol. 53, pp. 812-821, june 2004.

  185. A. N. Tikhonov and A. A. Samarskii, Equations of Mathematical Physics. Dover Publications, 2011.

  186. V. Huard, M. Denais, and C. Parthasarathy, "NBTI degradation: from physical mechanisms to modeling," Microel. Reliab., vol. 46, no. 1, pp. 1-23, 2006.

  187. T. Grasser, T. Achinger, G. Pobegen, H. Reisinger, P.-J. Wagner, J. Franco, M. Nelhiebel, and B. Kaczer, "The `permanent' component of NBTI: composition and annealing," in Conference Proceedings of International Reliability Physics Symposium (IRPS 2011), 2011.

  188. M. Houssa, M. Tuominen, M. Naili, V. Afanas'ev, A. Stesmans, S. Haukka, and M. M. Heyns, "Trap-assisted tunneling in high permittivity gate dielectric stacks," Journ. Appl. Phys., vol. 87, no. 12, pp. 8615-8620, 2000.

  189. T. Grasser, "Stochastic charge trapping in oxides: from random telegraph noise to bias temperature instabilities," Microel. Reliab., vol. 52, no. 1, pp. 39-70, 2011.

  190. C. Chen and T. Ma, "Direct lateral profiling of both interface traps and oxide charge in thin gate MOSFET devices," IEEE Trans. Electron Dev., vol. 45, no. 2, pp. 512-520, 1998.

  191. Y.-L. Chu, D.-W. Lin, and C.-Y. Wu, "A new charge-pumping technique for profiling the interface-states and oxide-trapped charges in MOSFETs," IEEE Trans. Electron Dev., vol. 47, no. 2, pp. 348-353, 2000.

  192. H. Reisinger, T. Grasser, C. Schlunder, and W. Gustin, "The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress," in Proc. International Reliability Physics Symposium (IRPS), pp. 7-15, 2010.

  193. B. Kaczer, T. Grasser, P. Roussel, J. Franco, R. Degraeve, L. Ragnarsson, E. Simoen, H. Reisinger, et al., "Origin of NBTI variability in deeply scaled pFETs," in Proc. International Reliability Physics Symposium (IRPS), pp. 26-32, 2010.

  194. V. Huard, M. Denais, F. Perrier, N. Revil, C. Parthasarathy, A. Bravaix, and E. Vincent, "A thorough investigation of MOSFETs NBTI degradation," Microel. Reliab., vol. 45, pp. 83-98, 1 2005.

  195. B. Bindu, W. Goes, B. Kaczer, and T. Grasser, "Analytical solution of the switching trap model for negative bias temperature stress," in Proc. International Integrated Reliability Workshop (IIRW), pp. 93-96, 2009.

  196. N. Stojadinovic, M. Pejovic, S. Golubovic, G. Ristic, V. Davidovic, and S. Dimitriev, "Effect of radiation-induced oxide-trapped charge on mobility in p-channel MOSFETs," Electronics Letters, vol. 31, no. 6, pp. 497-498, 1995.

  197. M. Abramowitz and I. Stegun, Handbook on mathematical functions. New York: Dover, 1972.


I. Starkov: Comprehensive Physical Modeling of Hot-Carrier Induced Degradation