Next: 1.3.3 HCD in Scaled Devices Up: 1.3 Characteristic Features of HCD Previous: 1.3.1 Different Nature of HCD Mechanisms
While the history of HCD in scaled MOSFETs has been rather dramatic, the situation around high voltage (HV) devices is equally challenging, i.e. this concern was and is one of the most severe problems in devices of this class. At present, the LDMOS and drain extended metal-oxide-semiconductor (DEMOS) are the most promising high-voltage devices commonly employed in display drivers, automobile and smart-power applications, because of their compatibility with the standard CMOS process [53,19,22,54,47,55,51,56,57,58,59,60,61,62,63]. The post-stress behavior of both CMOS and high-voltage devices displays many similarities:
The behavior of high-voltage devices under HC stress features many additional peculiarities. One of the most severe issues is the Kirk effect [77,78,58,59,60,61,62] resulting in a secondary substrate current Isub peak at high gate voltages Vgs (above ~30V) and, hence, in a strong degradation of the ON-state resistance [58,59,60,61]. The second one is the considerable HCD recovery [60,79,80,81,21] vs. a weak one observed in CMOS devices [82,83,84]). Due to this recovery the AC device lifetime is much higher than that in the DC regime. The degradation suppression under accelerated temperatures is still an ambiguous issue for high-voltage devices. In fact, the parasitic effect of self-heating (often strongly localized) drastically complicates the high-voltage device behavior under HC stress [19,73,79]. Additionally, the HCD picture for p-channel devices (no matter whether low- or high-voltage transistors are meant) is contaminated by an interplay with NBTI which shows the opposite temperature behavior [85,76,86,87].