2.5 Gate Leakage

As the continuous down-scaling of the device size has lead to very thin gate oxides, the leakage current that can flow from the channel to the gate comes into the order of the subthreshold leakage current and the gate cannot be considered as an ideally insulated electrode anymore. This affects the circuit functionality and increases the standby power consumption due to the static gate current. For dynamic logic concepts the gate leakage drastically reduces the maximum clock cycle time [67].

Two tunneling mechanisms are responsible for the gate leakage, Fowler-Nordheim tunneling and direct tunneling [47]. The gate leakage increases exponentially as the oxide thickness is reduced. This limits the down-scaling of the oxide thickness to about 1.5-2 nm when looking at the total standby power consumption of a chip [61]. To further decrease the effective oxide thickness alternative high dielectric constant materials can be used [64]. On the other hand, a thin gate oxide reduces the short-channel effect and improves the driving capabilities of a MOS transistor. However, a tradeoff between this benefit and the gate leakage is necessary.

Figure 2.9: Lateral electric field at the channel surface of Device $\beta$ in the on-state.