Contents

• List of Figures
• List of Tables
• 1. Introduction
  • 1.1 Semiconductor Roadmap
  • 1.2 Device Optimization Methods
  • 1.3 Outline of this Work
• 2. ULSI MOS Device Phenomena
  • 2.1 Subthreshold Leakage
  • 2.2 Punchthrough
  • 2.3 Drain-Induced Barrier Lowering
  • 2.4 Hot Carrier Effects
  • 2.5 Gate Leakage
• 3. Optimization Setup
  • 3.1 Device Description
    • 3.1.1 Device Geometry
    • 3.1.2 Source and Drain Doping
    • 3.1.3 The Makedevice Input Deck
    • 3.1.4 Two-Dimensional Doping Characterization
    • 3.1.5 Analytical Profiles
  • 3.2 Optimization Procedure
    • 3.2.1 Optimization Sequence
    • 3.2.2 SIESTA as the Optimization Environment
    • 3.2.3 Optimization Performance
• 4. Drive Current Optimization
  • 4.1 Target and Constraint Definition
  • 4.2 Optimizer Setup
  • 4.3 Simulator Setup
  • 4.4 Optimization Process
    • 4.4.1 Two-Dimensional Optimization
    • 4.4.2 Sensitivity Analysis
    • 4.4.3 Analytical Profiles
    • 4.4.4 Discussion
• 5. Peaking Channel Doping
  • 5.1 Transfer Characteristics
  • 5.2 Performance Enhancement Investigations
    • 5.2.1 Lateral Doping Peak Length
    • 5.2.2 Vertical Doping Peak Length
    • 5.2.3 Lateral Doping Peak Position
  • 5.3 Peak Parameters--A Qualitative Study
  • 5.4 Short Channel Effect
  • 5.5 Bulk Current
  • 5.6 Practical Considerations
  • 5.7 Alternative PCD Structures
• 6. Gate Delay Time Optimization
  • 6.1 Target and Constraint Definition
  • 6.2 Optimizer Setup
    • 6.2.1 Evaluation Network
    • 6.2.2 Infinite Inverter Chain Emulation
  • 6.3 Simulator Setup
  • 6.4 Optimization Process
    • 6.4.1 Two-Dimensional Optimization
    • 6.4.2 Sensitivity Analysis
    • 6.4.3 Analytical Profiles
    • 6.4.4 Discussion
  • 6.5 Ring Oscillator Verification
• 7. Summary and Outlook
• A. Drive Current as the Constraint
• B. Device Generator Makedevice
• C. Analytical MOS Model
• Bibliography