5.2.3 Lateral Doping Peak Position

At a first glance, the advantage of placing the doping peak close to the source may not be obvious. To investigate how the performance changes with the peak position a three-transistor model is created and the performance results achieved with this model are compared to the two-dimensional device simulation results.

A long PCD device is used to illustrate the effect of the peak position more clearly. This device is the result of a separate optimization process using the same geometry, source/drain doping, and supply voltage as for Device Generation A in Table 3.1, but with a long gate length of 1 $\mu$m.

Fig. 5.7 shows the device structure together with the three-transistor model. Transistor M2 has a fixed gate length and is equivalent to the doping peak, M1 and M3 represent the lightly-doped regions on the left and right sides of the peak, respectively. Their lengths can be adjusted to track the variable peak position.

Figure 5.7: A long PCD device and its three-transistor equivalent model.

The peak position is varied from the source to the drain side and the drive and leakage currents are simulated with MINIMOS-NT. The three-transistor model is calculated using the analytical drain-current model without DIBL. The model parameters are chosen to fit the results from the two-dimensional device simulations.

Table 5.2 gives a list of the model parameter values for the transistors used in the three-transistor model. The device characteristics can be either set by primary or secondary model parameters of the analytical model listed in Appendix C. For M1 and M3 the primary model parameters are used, for transistor M2 the secondary model parameters are used instead.

Table 5.2: Model parameters for the three-transistor model.

Transistors M1, M3			Transistor M2
parameter	value	unit	parameter	value	unit
$\mu _0$	1430	cm$^2$/Vs	$\mu$	250	cm$^2$/Vs
$N_{\mathrm{sub}}$	2.8$\cdot$10$^{15}$	cm$^{-3}$	$KP$	1.723$\cdot$10$^{-4}$	A/V$^2$
$t_{\mathrm{ox}}$	5	nm	$\phi$	0.834	V
$n_{\mathrm{i}}$	1.4$\cdot$10$^{10}$	cm$^{-3}$	$\gamma$	0.98	$\sqrt{V}$
$V_{\mathrm{contact}}$	$-$0.55	V	$V_{\mathrm{th,0}}$	0.68	V
$v_{\mathrm{sat}}$	$\infty$	cm/s	$E_{\mathrm{c}}$	$\infty$	V/cm
$L$	varying	$\mu$m	$L$	0.02	$\mu$m
$W$	1	$\mu$m	$W$	1	$\mu$m

A good correlation of the tendency of the drive and leakage currents can be observed for the numerical simulations and the three-transistor model, even though the exact values differ, as depicted in Fig. 5.8. When the doping peak comes closer to source or drain, it enters the depletion region of the drain well. Therefore, the drain current rises because of the reduced potential barrier between source and drain (DIBL). Furthermore, the peak doping is more and more neutralized by the high donor doping which reduces the threshold voltage. These effects are not covered by the three-transistor model.

Figure 5.8: Variation of the lateral doping peak position: (a, b) drive and leakage current from two-dimensional device simulation, (c, d) using the three-transistor model

While the leakage current remains rather constant, the drive current decreases as the doping peak moves towards drain. The reason can be found in the behavior of transistor M1 which works in the ohmic region and, therefore, as a series resistance to M2. When the source voltage of M2 rises due to the voltage loss over M1, the drive current decreases as the gate-source voltage of M2 becomes smaller. For the leakage current this effect cannot be observed because the drain current is too small to produce a significant voltage drop over M1.

It can be concluded from Fig. 5.8 that a peak position in the middle of the channel would still deliver an excellent drive current performance. This can be important if only symmetric devices are desired.