In order to find an explanation why the placement of a narrow doping peak in the channel of a MOS transistor improves its drive performance, the optimal geometry and placement of the peak are investigated. Basic guidelines for the lateral length of the doping peak are presented using a uniformly doped device with a gate length matching the doping peak length of the PCD device. An equivalent three-transistor model and a simple analytical drain-current model described in Appendix C provide the basis for the investigations.