6.4 Optimization Process

For the gate delay time optimizations the two-step approach introduced in Chapter 3 is taken. Accordingly, two-dimensional optimizations are performed first. Then, after the sensitivity analysis has been carried out, Gaussian functions are used to simplify the profiles.

For dynamic simulations of an inverter the drain-bulk capacitance influences the simulation results because it must be charged or discharged during inverter switching. This capacitance results mainly from the drain-bulk junction capacitance at the bottom and the sidewalls of the drain well. Usually the bottom capacitance is much higher than the sidewall capacitance, therefore the drain-bulk capacitance depends almost linearly on the junction area and thus on the lengths of the source and drain wells.

These lengths are chosen 4/3 of the gate length including the lengths of the spacers (1/3  $L_{\mathrm{g}}$) and the contacts ( $L_{\mathrm{g}}$). In practice the respective device geometry is subject to certain design rules which come with a specific process technology.