6.4.2 Sensitivity Analysis

To identify the relevant doping regions of the devices a sensitivity analysis is carried out. This procedure is explained in detail in Section 4.4.2. The results for Device Generation A are shown in Fig. 6.13 and Fig. 6.14, and for Device Generation B in Fig. 6.15 and Fig. 6.16. It can be seen that the gate delay time and leakage current sensitivities are almost identical. The most important region is once again the doping peak in the channel.

Figure 6.13: The gate delay time (top) and leakage current (bottom) sensitivities for the NMOS, Device Generation A.

Figure 6.14: The gate delay time (top) and leakage current (bottom) sensitivities for the PMOS, Device Generation A.

Figure 6.15: The gate delay time (top) and leakage current (bottom) sensitivities for the NMOS, Device Generation B.

Figure 6.16: The gate delay time (top) and leakage current (bottom) sensitivities for the PMOS, Device Generation B.