6.4.1 Two-Dimensional Optimization

For the two-dimensional gate delay time optimizations 124 optimization parameters are used to describe the doping profiles of the NMOS and PMOS transistors, 62 parameters for each of them. The same inverted-T structure as for the drive current optimizations (shown in Fig. 3.4) is utilized with the raised-cosine interpolation method described earlier in Section 3.1.4. The constant background substrate doping was kept at 10$^{15}$ cm$^{-3}$ for both devices.

The optimization starts with a uniformly doped inverted-T region. First a self-consistent initial state has to be found. This means that a set of input V-t and load C-V curves has to be provided which reflects a situation as if this initial inverter was part of an infinite inverter chain. Therefore, the input V-t and load C-V curves evaluated from the inverter output V-t curve using the time-shift method described above, and the input I-t curves using (6.1), respectively, have to reach a steady state.

This is achieved by the stand-alone procedure shown in Fig. 6.7 which is performed before the optimization starts. Alternately, the on- and off-transitions of the inverter are simulated and the input V-t and load C-V curves are evaluated in a post-processing step and updated after each simulation. After a couple of steps the stationary condition is reached and the stand-alone procedure can be terminated. Then the actual optimization is started.

Figure 6.7: The stand-alone procedure to provide a self-consistent initial state for the gate delay time optimizations.

Fig. 6.8 shows the improvement of the average inverter delay time during the optimization procedure for both device generations. The values are taken at each temporary minimum meaning the last evaluation step before the gradient calculations as shown in Fig. 6.5. The constraint was fulfilled at any time, so the average leakage current is kept at 1 pA. The whole optimization procedure takes about one day up to a few days depending on the number of available machines in the workstation cluster.

Due to the fact that the number of optimization parameters has doubled compared to drive current optimizations, the number of total simulation jobs has also increased by about a factor two. This has increased the computational effort, but the main reason for the drastically increased optimization time can be found somewhere else: Transient simulations obviously require much more time than single operating point calculations.

This complex gate delay time optimization gives an impressive example of the capabilities of the SIESTA optimization framework. It is not a straightforward task to handle more than 100 optimization parameters and maintain a stable optimization environment which runs a couple of days in a row on a workstation cluster. This task could not have been successfully finished without the fault tolerance and the load balancing capabilities of SIESTA.

Figure 6.8: The inverter delay time improvement during optimization.

Fig. 6.9 and Fig. 6.10 show the acceptor doping profiles of the NMOS and PMOS transistors, respectively, as the result of the two-dimensional optimization approach for Device Generation A. Fig. 6.11 and Fig. 6.12 show the respective profiles for Device Generation B.

Figure 6.9: The result of the two-dimensional gate delay time optimization for the NMOS, Device Generation A.

Figure 6.10: The result of the two-dimensional gate delay time optimization for the PMOS, Device Generation A.

Figure 6.11: The result of the two-dimensional gate delay time optimization for the NMOS, Device Generation B.

Figure 6.12: The result of the two-dimensional gate delay time optimization for the PMOS, Device Generation B.