6.4.4 Discussion

The inverter characteristics for the various optimizations performed are summarized in Table 6.3. Please note that the performance gains are calculated from the inverse of the average delay time which is a metric for the speed of the inverter. They refer to uniformly doped devices with a bulk doping concentration of 5.53$\cdot$10$^{17}$ cm$^{-3}$ (NMOS) and 4.75$\cdot$10$^{17}$ cm$^{-3}$ (PMOS) for Device Generation A and 2.04$\cdot$10$^{18}$ cm$^{-3}$ (NMOS) and 1.80$\cdot$10$^{18}$ cm$^{-3}$ (PMOS) for Device Generation B, respectively. The optimization results using a one-dimensional approach in the vertical direction are shown, too.

Table 6.3: Comparison of the inverter characteristics and performance gains.

	$I_\mathrm{off,NMOS}$	$I_\mathrm{off,PMOS}$	$t_\mathrm{d,on}$	$t_\mathrm{d,off}$	$t_{\mathrm d}$	perf. gain
	(pA)	(pA)	(ps)	(ps)	(ps)
Device Generation A
uniformly doped	1.0	1.0	63.1	44.3	53.7	-
one-dimensional vertical	1.0	1.0	45.8	30.2	38.0	41.1%
two-dimensional	1.3	0.7	40.9	28.8	34.9	53.9%
one Gaussian function	1.2	0.8	41.4	29.2	35.3	52.1%
two Gaussian functions	1.3	0.7	41.1	28.9	35.0	53.4%
Device Generation B
uniformly doped	1.0	1.0	78.0	66.9	72.5	-
one-dimensional vertical	0.9	1.1	46.1	38.0	42.0	72.6%
two-dimensional	1.0	1.0	39.1	34.5	36.8	97.0%
one Gaussian function	1.0	1.0	42.1	35.9	39.0	85.9%
two Gaussian functions	1.1	0.9	41.1	35.1	38.1	90.3%

Fig. 6.25 and Fig. 6.26 show the vertical doping profiles after the one-dimensional optimization for Device Generation A and Device Generation B, respectively. Only vertical doping variations were allowed in the inverted-T region already used for the two-dimensional approach.

Figure 6.25: The gate delay time optimization results of the purely vertical optimization for the NMOS (top) and PMOS (bottom), Device Generation A.

Figure 6.26: The gate delay time optimization results of the purely vertical optimization for the NMOS (top) and PMOS (bottom), Device Generation B.

The inverter V-t curves for the uniformly doped device and the two-dimensional optimization results are depicted in Fig. 6.27 for both Device Generation A and Device Generation B. The delay times for the on-transitions of the output node $t_\mathrm{d,on}$ are higher than the ones for the off-transitions $t_\mathrm{d,off}$ which is illustrated in Table 6.3, and can be explained as follows: The performed optimizations delivered fairly equal leakage currents for both the NMOS and PMOS transistors, therefore, the PMOS devices have lower drive currents than the NMOS devices due to the lower carrier mobility of holes compared to that of electrons.

Figure 6.27: Input (dashed) and output (solid) curves of the two-dimensional optimization results compared to the uniformly doped device for Device Generation A (top) and Device Generation B (bottom).

The performance improvements due to gate delay time optimizations listed in Table 6.3 are much higher than one would have predicted considering the results from drive current optimizations given in Table 4.4. Obviously, the improved drive current is not the only reason for the increased inverter speed. The decreased device capacitances, mainly the drain-bulk junction capacitance, also contribute to the enhanced inverter characteristics.

Fig. 6.28 shows an equivalent small-signal model of the CMOS inverter [65], the device capacitances are drawn separately. Investigating the inverter input C-V curves has shown that the total input capacitance stays almost constant during optimization and does hardly contribute to the improved performance. This capacitance consists of the gate-source capacitances C$_\mathrm{gs}$, $\tilde{\mathrm{C}}_\mathrm{gs}$, the gate-drain capacitances C$_\mathrm{gd}$, $\tilde{\mathrm{C}}_\mathrm{gd}$ which add up twice due to the Miller effect [67], and the gate-bulk capacitances C$_\mathrm{gb}$, $\tilde{\mathrm{C}}_\mathrm{gb}$.

Figure 6.28: The small signal inverter model.

The capacitances which are drastically reduced by optimization are the drain-bulk junction capacitances C$_\mathrm{db}$ and $\tilde{\mathrm{C}}_\mathrm{db}$. The capacitance of a reverse biased p-n junction strongly depends on the doping levels on both sides of the junction and the applied voltage. In case of a drain well the junction can be approximated by a one-sided junction as the drain is heavily doped. The drain-bulk capacitance per unit area can then be calculated by

$$C_\mathrm{db}' = \sqrt{\frac{q \cdot \epsilon_\mathrm{si} \cdot N_\mathrm{bulk}}{2 \cdot \vert V_\mathrm{db}+\phi_0\vert}}$$ (6.8)

where $q$ denotes the electron charge, ${\epsilon}_{\mathrm{si}}$ the permittivity constant in silicon, $N_\mathrm{bulk}$ the bulk doping level, $V_\mathrm{db}$ the drain-bulk voltage, and $\phi_0$ the built-in potential of the junction [65].

The lighter background doping of the optimized devices provides a much smaller drain-bulk capacitance compared to the uniformly doped devices which reduces the total capacitance at the output node of the inverter and, therefore, the delay time.

A direct comparison of the doping profiles obtained from drive current and gate delay time optimizations is not possible here because the maximum drive current during an inverter transition occurs at a time when the input voltage has not reached the supply voltage yet and the output voltage has already started to fall. Therefore, the operating conditions are different for the two cases since for the drive current optimizations the on-state was simulated with gate and drain connected to the supply voltage (see Fig. 4.1).

This behavior is depicted in Fig. 6.29 for an off-transition of the optimized inverter using devices of Generation A. It shows the input and output V-t curves and the drain current of the NMOS transistor of Fig. 6.2. The gate voltage of the transistor at the time when the maximum drain current occurs is 1.22 V and the drain voltage is 0.53 V.

Consequently, the optimum doping peak for the maximum gate delay in Fig. 6.17 is slightly longer than the one for the maximum drive current in Fig. 4.8. This has already been predicted in Section 5.3 where optimizations with different supply voltages resulted in an increased peak length. The position of the right peak edge $x_0+\Delta x+\sigma_x$ was used as a metric. Considering that in this chapter the source and drain wells are by 2/3 of the gate length longer, the equivalent position results to 0.2637 $\mu$m which lies exactly between the values 0.2728 $\mu$m and 0.2551 $\mu$m given in Table 4.4 for 1 V and 1.5 V supply voltages, respectively.

Figure 6.29: The voltage and current conditions of the NMOS transistor during an off-transition.