6.5 Ring Oscillator Verification

The presented gate delay time optimization method is based on the realistic case of the inverter being used in an ensemble of inverter stages which can be found, for example, in an infinite inverter chain or a ring oscillator circuit.

To verify that the resulting delay times using the single stage inverter model of Fig. 6.2 are realistic values, a five stage ring oscillator circuit (Fig. 6.30) is simulated using mixed-mode transient simulations. The initial state forces an unbalanced condition for the inverter at the right end of the chain starting the oscillation. This rather complex simulation task can be performed thanks to the rigorous mixed-mode simulation capabilities of MINIMOS-NT [22].

Figure 6.30: The five stage ring oscillator with its initial state.

The node voltages of the ring oscillators using uniformly doped devices and devices with optimized doping profiles (two-dimensional approach) are depicted in Fig. 6.31 and Fig. 6.32 for Device Generation A and Device Generation B, respectively.

Figure 6.31: The node voltages of a five stage ring oscillator using uniformly doped devices (top) and devices with optimized doping profiles (bottom) for Device Generation A.

Figure 6.32: The node voltages of a five stage ring oscillator using uniformly doped devices (top) and devices with optimized doping profiles (bottom) for Device Generation B.

The average gate delay time of a ring oscillator $t_{\mathrm d}$ is calculated from its oscillation frequency $f_0$ by

$$t_\mathrm{d} = \frac{1}{2\cdot n\cdot f_0}$$ (6.9)

with $n$ being the number of stages.

Table 6.4 compares the calculated ring oscillator gate delay times with the results obtained from the infinite inverter chain emulations using the single stage inverter model. The ring oscillator delay times are all slightly above the single stage delay times. This results from tailoring the overshoot in the input V-t curves as explained in Section 6.2.2. However, the single inverter stage model has proven to be a very good approximation for the realistic case that occurs in a digital circuit. For optimization purposes a correct qualitative behavior of a model is the primary concern because the goal is to improve a certain performance metric.

Table 6.4: Comparison of the gate delay times of the ring oscillator to the single stage inverter model

	Device Generation A		Device Generation B
	ring oscillator	single stage	ring oscillator	single stage
uniformly doped	55.3 ps	53.7 ps	74.3 ps	72.5 ps
two-dimensional	35.4 ps	34.9 ps	38.9 ps	36.8 ps