7. Summary and Outlook

It has been shown in this work that automated closed-loop optimizations of MOS doping profiles lead to a drastically improved device performance. The optimizations were performed using a numerical device simulator (MINIMOS-NT) within a recently developed TCAD optimization framework (SIESTA).

Two different device generations for portable electronics with their special ultra low-power requirements were compared, one with 0.25 $\mu$m gate length as the state-of-the-art generation, the other one with 0.1 $\mu$m gate length as the generation which will emerge during the next years. The device geometries and the source and drain doping profiles were chosen in accordance with the recommendations of the SIA roadmap focusing on low-power technologies and were kept fixed during the optimizations.

Two different approaches were taken to define the doping profile in the bulk. The first one was a fully two-dimensional approach using an optimization grid in a discretization region with the shape of an inverted-T. The optimization parameters were the doping concentrations at the grid points. A raised-cosine interpolation method was used to receive the two-dimensional doping distribution.

After this very general approach the set of optimization parameters was drastically reduced after the important doping regions were pointed out by a sensitivity analysis of the optimization result. A second approach was utilized using Gaussian functions and a new optimization procedure was launched. The very complex results of the two-dimensional approach could successfully be tailored using Gaussian functions.

This two-stage procedure was first applied to drive current optimizations of a single NMOS transistor with constrained drain-source leakage. The resulting doping profiles for both device generations feature a narrow doping peak in the channel close to the source. The drive current improvements of these PCD devices compared to a uniformly doped device were up to 45% for the 0.25 $\mu$m device and up to 71% for the 0.1 $\mu$m device.

Explanations for the superior performance of the PCD device were given by variation of the geometry and the position of the doping peak. It turned out that the PCD reduces the effective gate length of the transistor and thereby increases the ratio between the on- and off-currents.

A qualitative study was performed to obtain design guidelines for the doping peak under different supply voltage and leakage current conditions. The lateral peak length showes a dependence on the applied gate voltage.

Further benefits were pointed out, namely the reduced hot carrier effects due to a reduction of the lateral electric field and the improved $V_{\mathrm{th}}$ roll-off due to the highly localized peak doping at the source side. Practical considerations showed that the gap between the very theoretical optimization results and manufacturable solutions can be bridged. Though some realistic structures proposed could not reach the high performance gain of the standard PCD device their performance was still substantially higher that that of a uniformly doped device or a transistor with purely vertical channel profile engineering.

This optimization procedure was extended to a complete CMOS inverter stage with the doping profiles of the NMOS and PMOS devices being optimized at the same time using transient numerical simulations. The goal was to minimize the average inverter delay time while keeping the average leakage current below the a limit suitable for ultra low-power applications. To emulate the behavior of the inverter stage inside a complete digital circuit a method was introduced using input and output data of the inverter to evaluate the input curves and load conditions for the following simulations.

The results were, again, PCD devices though the doping profiles slightly differe from the ones obtained by drive current optimizations due to the changed operating condition during inverter switching. To verify that the delay times of the optimized inverter stages really match with the realistic case inside a circuit, ring-oscillators were simulated and the correspondence was very good. The speed improvements were up to 54% for the 0.25 $\mu$m device and 97% for the 0.1 $\mu$m device compared to a uniformly doped device. The enhanced performance was attributed to the increased drive currents and the reduced drain-bulk junction capacitances.

Generally, this work has shown that a non-uniform channel doping in both the lateral and vertical direction must be provided if the device shall have optimal driving performance. Furthermore, a clearly asymmetric doping profile with the doping peak at the source side delivers the best results, though symmetric structures can still have a very good performance.

All investigations were based on low-power technologies with a focus on high-performance portable systems. This was achieved by assuming a very low leakage current of 1 pA per $\mu$m gate width. If these optimizations were performed on technologies for desktop applications, the resulting doping profiles might be different, especially in the vertical direction. This is because the bulk effect will lose importance as the devices only reach the onset of the weak inversion regime when turned off. Therefore, a higher background doping would be allowed which can even lead to Retrograde Channel Profiles (RCP), in the extreme case [16].

Due to its flexibility, the presented optimization procedure can be applied to a huge number of different optimization tasks, not only for semiconductor applications, but in all fields of science where numerical simulation can be used to predict a system's performance. It has been shown that, even with a very large number of optimization parameters, the framework stays stable and immune against network errors.

When computer systems will become much faster in the near future, especially thanks to automated optimizations on the device and circuit levels, the analytical device generator in the optimization loop can be substituted by complete process simulations providing a direct link between the optimization parameters and the various process parameters in a fabrication facility. The first steps have already been taken into this direction [55], but the number of process parameters which can be optimized simultaneously is still poor and will increase drastically in the future.

Since the scalability of device performance cannot keep track with the fast scaling of its geometry, new methods have to be found besides standard technologies to satisfy the needs of the semiconductor industry. The PCD device offers the chance to drastically improve the device performance by doping engineering and is, therefore, a good candidate for future device generations.