6. Gate Delay Time Optimization

Today high speed operation and reduced standby power consumption are key challenges of devices for the ever increasing portable electronics market. In CMOS digital circuits with static logic the average gate delay time of a simple inverter chain, as shown in Fig. 6.1, provides a useful metric for the overall circuit speed.

Figure 6.1: An infinite CMOS inverter chain.

On a test chip a ring oscillator circuit is often used which consists of a finite inverter chain with its output fed back to the input. There has to be an odd number of inverter stages in this case to guarantee the required negative feedback. By determining the oscillating frequency of a ring oscillator one can calculate the average gate delay time of one respective inverter stage.

There are several aspects which have to be considered when trying to improve the gate delay time. First of all, the drive currents of the transistors should be as high as possible to make fast charging and uncharging of the circuit nodes possible, as already mentioned in the beginning of Chapter 4. Furthermore, the involved capacitances, either intrinsic or extrinsic, have to be low to reduce the amount of charge being transferred to or from the nodes.

The supply voltage is usually not a design parameter for a given technology. Anyway, the node charge is directly proportional to it. Thus, lowering the supply voltage seems to be appropriate, but this will, on the other hand, reduce the driving capabilities of the transistors due to a reduced gate voltage.

It has been shown in Chapter 4 that the drive current can be drastically increased by automated doping profile optimization. In this chapter the same optimization procedure is applied, but this time with a different goal, namely to minimize the inverter gate delay time. Since the doping profile not only influences the static currents of a MOS transistor, but also the intrinsic capacitances and, therefore, the dynamic behavior, it will be interesting to see if the resulting profiles show new features compared to the results from the static drive current optimizations.

For simulation purposes the minimum gate length is used and the width is set to 1 $\mu$m for both the NMOS and PMOS transistors. In integrated circuits the minimum gate width will be chosen to minimize the device area and, therefore, the required chip size. Anyway, the currents and capacitances can be scaled according to the gate width.