Fig. 6.3 shows the evaluation network for the gate delay time
optimizations. After reading a given set of optimization parameters, the
device descriptions of both the NMOS and PMOS transistors are generated with
Makedevice and written on PIF files. Then two transient device simulations are
carried out, one for the on-transition, the other for the off-transition of
the single inverter stage of Fig. 6.2. Additional input data,
besides the device descriptions, are taken from a data container including the
input V-t curves of the inverter and the C-V curves of the capacitive load
,
both for the two transition cases.
With the simulated output V-t and the transistors'
-t curves, the delay
times and leakage currents are calculated in a post-processing step. To find
the delay times, the time-points when the inverter's input and output V-t
curves cross the
/2 mark are extracted and subtracted from each other.
This is done using a script which also delivers the leakage currents taking
advantage of the fact that the cross-current of the inverter stage at the
beginning of the transient simulation is exactly the leakage current of one of
the transistors, depending on which transition case is simulated. Finally,
the target and constraint are evaluated using (6.2) and
(6.3).