3.1.1 Device Geometry

A quite simple device geometry is used throughout this work (see Fig. 3.2). It is a planar structure with SiO$_2$ source and drain spacers and an SiO$_2$ gate insulator. The bulk contact is at the bottom of the device. The bulk layer was chosen thick enough so that the depletion region under the channel is small in comparison.

For simplicity an ideal conductor is used as the gate material, but a polysilicon gate is modeled by accounting for the work function difference between metal and polysilicon in the simulator setup. The polysilicon doping is assumed to be a result from a common dual gate process where it is highly doped with the same kind of dopands as source and drain. The effective gate oxide thicknesses (listed in Table 3.1) already account for quantum mechanical effects at the channel surface displacing the centroid of the channel charge distribution from the interface [19,54] and for polysilicon depletion effects [27].

Figure 3.2: The used device geometry.