First a review of ULSI MOS device phenomena is presented in Chapter 2. The described phenomena will be important throughout the remainder of this work. Their impact on the device characteristics and how they can be controlled is investigated.
An optimization setup is described in Chapter 3. The device
descriptions for two device generations with 0.25 
m and 0.1 m gate
lengths, respectively, are given and two different approaches to define a
variable doping profile are introduced: one using a two-dimensional
optimization grid, the other one using Gaussian functions. The optimization
parameters are determined for both methods. Then the optimization procedure
using SIESTA as the optimization environment is explained. Special
emphasis is laid on the performance of the optimization with respect to the
required computation time and the stability which can be achieved.
In Chapter 4 the doping profiles of NMOS transistors are optimized with respect to their drive currents. The leakage currents are kept below a certain limit to meet the requirements of ultra low-power applications. The setup of the SIESTA framework and the device simulator for this specific optimization task are explained in detail. After two-dimensional doping optimizations based on a tensor grid representation of the doping profile, the results are valued by a sensitivity analysis. The important doping regions are identified and substituted by Gaussian functions and further optimizations are performed. As a result, a new device doping structure is found which has a peak doping at the channel surface close to the source well and a drastically improved driving capability compared to a uniformly doped device. It is denoted ``Peaking Channel Doping (PCD) device'' in this work.
Chapter 5 investigates the characteristics of the PCD device and explains its enhanced drive performance. A qualitative study is carried out finding design guidelines for the PCD device under different supply voltage conditions and leakage current constraints providing a deeper insight into its superior performance. Further benefits of the new PCD structure are pointed out looking at its hot carrier and short channel effects (SCE). Practical considerations give possible solutions for the manufacturing of the PCD device and compare them with already existing device architectures.
In Chapter 6 the gate delay times of complete CMOS inverters are optimized by doping profile optimizations of the involved NMOS and PMOS transistors. Transient numerical device simulations are utilized to determine the average switching speed of the inverters. This time the average leakage current is kept below a certain limit. The used inverter stage model emulates the behavior of an infinite inverter chain. This is achieved by providing a realistic input voltage and load capacitance evaluated from the simulation results of previous optimization steps. The two-dimensional optimization approach is followed by a sensitivity analysis of the doping parameters and further optimizations using Gaussian functions. The PCD device structure is also found optimal to improve the delay time of an inverter. The optimization results are verified by simulations of ring oscillator circuits confirming that the assumptions made about the infinite inverter chain have been correct.
A summary and outlook conclude this work in Chapter 7.