During the last decades low-voltage/low-power applications are becoming more and more important because of the increasing portable electronics market. The emerging rush to mobile communications including voice, picture, and data transfer and the need of mobile computers which have almost the same performance as their immobile counterparts are advancing the continuous improvement of low-power high-performance integrated circuits [1,4,5,20,25].
A subscriber unit of a mobile phone, for example, spends typically most of its time in the stand-by mode, so that its stand-by power must be kept below a specified value to maximize the battery lifetime. On the other hand, when a communication takes place, the unit must perform high speed computations; it will de-compress the incoming signal and compress the outgoing signal.
Due to the fact that the energy density of commonly used batteries is limited, they have become a bottleneck in reducing the weight of portable devices. Therefore, saving weight can only be achieved by reducing the total power consumption. This is contrary to the fast growing number of devices on a chip due to the increasing system complexity (see Section 1.1). Therefore, the power problem has to be solved on the transistor and circuit levels [11,21,32].
Ultra Large Scale Integration (ULSI) CMOS technology is perfectly suitable for the requirements of portable electronics due to its scalability and low power consumption. Various new MOS device architectures have been recently reported with channel lengths down to the nanometer range [69], but no general investigation has proven that one of these structures is optimal to meet a certain performance goal.
The system requirements for portable electronics are best met by MOS circuits featuring a restricted drain-source leakage current of the single transistors and highest possible switching speed. To accomplish this the devices have to be optimized for these specifications.
Usually, for a given device technology generation, the minimum feature size, gate oxide thickness, and supply voltage are implicitly defined. It will be shown in this work that the doping profile offers the chance to optimize the device characteristics since it determines the ``inner functioning'' of a MOS transistor, and is, therefore, the key to a higher device performance.
The question arises, ``What is the best doping profile for a given device technology and performance goal?'' Though this is a very theoretical question ignoring all manufacturability issues, the answer to this question can give valuable ideas to improve existing technologies or can even encourage the development of completely new device concepts.
The numerical simulation of integrated devices offers the possibility to optimize certain device properties by variation of the doping profile. This optimization procedure could never be possible using test wafers without limiting the optimization by manufacturability concerns at an early stage. Furthermore, optimizations with test wafers require a large number of runs and, therefore, involve high costs.
Optimizations performed ``by hand'' or manually controlled simulations are not suitable for complex optimization tasks like doping profile optimizations. Therefore, a TCAD framework offering fast automatic optimization by simulation (SIESTA) is used [55].
The optimizations are performed on devices with 0.25 
m and 0.1 m
gate lengths so that the optimal doping profiles of an existing device
generation and a future generation can be compared. The effective gate oxide
thicknesses of 5 nm and 2.5 nm, respectively, are chosen according to the
``National Technology Roadmap for Semiconductors'' (see Section 1.1). The
supply voltages given in this roadmap refer to desktop applications. For
portable electronic equipment the supply voltage is usually further
reduced [11,48], therefore numbers smaller than the ones given in
the roadmap are chosen (1.5 V and 0.9 V, respectively).