When Gordon E. Moore presented his vision about the future exponential growth of the semiconductor industry in 1965 known today as ``Moore's Law'' nobody would have expected it to hold for more than 30 years. It was not only about forecasting, but about commanding the silicon revolution [8]. This idea has become a more specific definition--a roadmap--giving guidelines how the development of semiconductors shall proceed during the next couple of years.
Since the ``National Technology Roadmap for Semiconductors'' has been published by the Semiconductor Industry Association (SIA) in 1992 with new versions in 1994, 1997 and 1999, it was widely quoted throughout the industry. During the years it has become the global industry's metronome, setting the tempo for the development of new semiconductor technologies. Due to the fast-paced nature of the industry there has been the need to review the roadmap annually.
Table 1.1 gives some important characteristics of the 1999 roadmap [49]. The gate length and the gate oxide thickness of MOS transistors will drastically shrink during the next years and the supply voltage will be reduced. At the same time the maximum power will not increase very much while the total number of transistors on a chip being the product of the transistor's density and the chip size will rise enormously. It is noteable, though not transparent to me, that the maximum chip power for portables predicted by the SIA will constantly rise until it reaches 2.4 W in 2005, then falls back to 2 W in 2008, and starts rising again.
| year | 1999 | 2002 | 2005 | 2008 | 2011 | 2014 | |
| technology generation |  m |
0.18 | 0.13 | 0.10 | 0.07 | 0.05 | 0.035 |
| dense lines: DRAM half pitch | m |
0.18 | 0.13 | 0.10 | 0.07 | 0.05 | 0.035 |
| isolated lines: MPU gate length | m |
0.14 | 0.85-0.9 | 0.065 | 0.045 | 0.03-0.032 | 0.02-0.022 |
| equivalent gate oxide thickness | nm | 1.9-2.5 | 1.5-1.9 | 1-1.5 | 0.8-1.2 | 0.6-0.8 | 0.5-0.6 |
| nominal S/D extension junction depth | nm | 42-70 | 25-43 | 20-33 | 16-26 | 11-19 | 8-13 |
| supply voltage, desktop | V | 1.5-1.8 | 1.2-1.5 | 0.9-1.2 | 0.6-0.9 | 0.5-0.6 | 0.3-0.6 |
| maximum power, high performance | W | 90 | 130 | 160 | 170 | 174 | 183 |
| maximum power, portables | W | 1.4 | 2 | 2.4 | 2 | 2.2 | 2.4 |
| substrate diameter | mm | 200 | 300 | 300 | 300 | 300 | 450 |
| MPU logic transistors density | cm |
6.6 M | 18 M | 44 M | 109 M | 269 M | 664 M |
| MPU chip size | mm |
340 | 356 | 408 | 468 | 536 | 615 |
The reduced geometry and supply voltage in conjunction with the demand to keep the performance of the devices high call for new solutions which are still unknown for the year 2008 and beyond while solutions for the year 2002 are already being pursued and widely discussed in the literature with all their problems involved [3,7,61,62,63,64,75]. New methods and technologies have to be developed and decisions have to be made about which of these new technologies will lead us to the desired goals.
While the semiconductor industry more or less sticks to the very precise predictions of the SIA roadmap, the development of totally new concepts might be ignored. With no clear successor to CMOS technology looming, CMOS should dominate the marketplace into the next century. But as we approach the physical limits of conventional technologies, as shown in the roadmap, the end of the ``great device shrink'' appears to be at hand. Therefore, it is appropriate to speculate about the future of electron devices.
The use of alternative technologies, for instance single-electron transistors will become increasingly important in the future. Their advantages are good scalability, ultra low-power operation, and high speed operation [76]. But there are still many unsolved problems with this new technology as demonstrated in [31].