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Using layer transfer and wafer bonding techniques, global strain can also be integrated on SOI substrate (see Figure 2.2). Electron and hole mobility enhancement comparable with the enhancement of wafers without the insulating layer were observed in ultra-thin strained Si layers on SiGe on insulator (SSGOI, Figure 2.2b) [Cheng01,Ghyselen04,Sadaka04,Andrieu06] and strained Si layers directly on insulator (SSDOI, Figure 2.2c) [Huang01,Rim03].
Technologies using ultra thin strained Si directly on insulator (SSDOI) are especially promising, since in those structures the SiGe layer is eliminated before transistor fabrication, hence critical process-integration problems related to the SiGe layer can be avoided. Among the difficulties of SSGOI are:
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Lately, an alternative back-end approach was proposed, where strain is introduced after the wafer has been completely processed [Belford01,Haugerud03]. The process starts with thinning the processed wafer to less than 10 µm, transferring it to a polymer film and then mechanically straining the Si membrane. This technique allows the introduction of biaxial and uniaxial strain parallel to the substrate surface without inducing defects in the Si layer. Within the elastic limit, the wafer can be safely mechanically strained and then bonded to a final substrate. At ultra-low strain levels (0.031%), holes in p-channel MOSFETs showed an increase in effective mobility of 14.35% and an enhancement in saturation current of 14.56%. An improvement in mobility of 18.49% and in saturation current of 18.05% was observed for n-channel MOSFETs strained by 0.052% [Haugerud03]. This relatively new method is promising as it is cost effective, however some yield and reliability issues have to be resolved before it can be used for full-scale IC manufacturing [Bera06].
A major drawback common to all global strain techniques for CMOS technology is that they can provide only one type of strain. Since the mobilities of electrons and holes are differently affected by strain, a global strain configuration, for example, compressive biaxial strain, can be beneficial for p-channel MOSFETs, but deteriorate the n-channel MOSFET performance. This problem is circumvented by local strain techniques, which are able to provide different strain patterns in n-channel- and p-channel MOSFETs.
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