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2.1 Global Strain Techniques

Most of the pioneering work on strained Si was focused on biaxial global strain generated by epitaxial growth of a thin Si layer on a relaxed SiGe virtual substrate [Welser92,Welser94]. Because of the lattice mismatch between Si and SiGe, the lattice of the Si layer is biaxially tensile strained in the plane of the interface. On {001} oriented substrates this deformation results in enhanced carrier transport in the strained Si layer, and mobility enhancements of 110% for electrons and 45% for holes have been demonstrated on sub-100 nm strained Si MOSFETs [Rim02].

Using layer transfer and wafer bonding techniques, global strain can also be integrated on SOI substrate (see Figure 2.2). Electron and hole mobility enhancement comparable with the enhancement of wafers without the insulating layer were observed in ultra-thin strained Si layers on SiGe on insulator (SSGOI, Figure 2.2b) [Cheng01,Ghyselen04,Sadaka04,Andrieu06] and strained Si layers directly on insulator (SSDOI, Figure 2.2c) [Huang01,Rim03].

Technologies using ultra thin strained Si directly on insulator (SSDOI) are especially promising, since in those structures the SiGe layer is eliminated before transistor fabrication, hence critical process-integration problems related to the SiGe layer can be avoided. Among the difficulties of SSGOI are:

An enhanced diffusion rate of dopants (B, As) in SiGe [Uppal04].
Significant device self-heating is observed in SSGOI devices because of the lower thermal conductivity of SiGe [Rim00].
SiGe strain relaxation induces a high density of defects in the neighboring strained Si layer [Fitzgerald91].
The thermal budget window for SGOI is smaller due to Ge up-diffusion from the underlying SiGe layer [Cheng01].

**Figure 2.2:** Schematic plot of strained Si MOSFETs using global strain: a) strained Si on SiGe on bulk wafer; b) strained Si on SiGe on insulator (SSGOI); c) strained Si directly on insulator (SDGOI).
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Lately, an alternative back-end approach was proposed, where strain is introduced after the wafer has been completely processed [Belford01,Haugerud03]. The process starts with thinning the processed wafer to less than 10 µm, transferring it to a polymer film and then mechanically straining the Si membrane. This technique allows the introduction of biaxial and uniaxial strain parallel to the substrate surface without inducing defects in the Si layer. Within the elastic limit, the wafer can be safely mechanically strained and then bonded to a final substrate. At ultra-low strain levels (0.031%), holes in p-channel MOSFETs showed an increase in effective mobility $\mu_\mathrm{eff}$ of 14.35% and an enhancement in saturation current of 14.56%. An improvement in mobility of 18.49% and in saturation current of 18.05% was observed for n-channel MOSFETs strained by 0.052% [Haugerud03]. This relatively new method is promising as it is cost effective, however some yield and reliability issues have to be resolved before it can be used for full-scale IC manufacturing [Bera06].

A major drawback common to all global strain techniques for CMOS technology is that they can provide only one type of strain. Since the mobilities of electrons and holes are differently affected by strain, a global strain configuration, for example, compressive biaxial strain, can be beneficial for p-channel MOSFETs, but deteriorate the n-channel MOSFET performance. This problem is circumvented by local strain techniques, which are able to provide different strain patterns in n-channel- and p-channel MOSFETs.

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E. Ungersboeck: Advanced Modelling Aspects of Modern Strained CMOS Technology