2.2 Local Strain Techniques

Various CMOS fabrication processes can be exploited to induce strain in the transistor channel (see Figure 2.1). Since these processes generate local strain that depends on the position in the MOSFET channel, techniques based on process-induced strain are frequently called local strain techniques.

Starting from the late 1990's effects related to local stress arising from various process steps on the performance of MOSFETs were investigated. It was found that mainly the following process steps are responsible for stress in the transistor channel:

• shallow trench isolation (STI) [Scott99,Matsumoto02]
• silicidation at the source/drain region [Steegen99]
• nitride contact etch stop liners (CESL) [Ito00,Shimizu01]

Even though process-induced strain initially was not able to provide as large strain levels as global strain, the local techniques enjoy three main advantages: (i) strain can be independently tailored to optimize performance enhancement for both n-channel- and p-channel MOSFETs, (ii) the threshold voltage shift is smaller in uniaxially stressed MOSFETs [Lim04], and (iii) local stress techniques are cheaper and more compatible with standard CMOS technology [Khamankar04].

The main challenge is to optimize process modules so as to maximize beneficial effects from stressors while minimizing negative side effects. A drawback of process-induced strain techniques is their strong device geometry dependence, making their scaling behavior less predictable [Eneman05].

Four important stress-transfer techniques will be discussed in the following: (i) the contact etch stop liner technique (CESL); (ii) the stress memorization technique (SMT); (iii) a technique based on selective epitaxial growth (SEG) of the source/drain regions, and (iv) stress from shallow trench isolation (STI).

Subsections

• 2.2.1 Contact Etch Stop Liner Technique
• 2.2.2 Stress Memorization
• 2.2.3 Selective Epitaxial Growth Technique
• 2.2.4 Stress from Shallow Trench Isolation

E. Ungersboeck: Advanced Modelling Aspects of Modern Strained CMOS Technology