2.3 Strain Technologies used in High Volume Production

Since the local strain approach turned out to be more promising for industrial applications, the first strain technologies used in high volume production were developed on the basis of uniaxial process-induced stress.

Starting from the 90 nm node, companies such as IBM [Ouyang05], Intel [Thompson04], Texas Instruments [Chidambaram06], and Freescale [Zhang05], incorporated the selective epitaxial growth technique to transfer uniaxial compressive stress into the Si channel by growing a local epitaxial film of SiGe in the source and drain region of p-channel MOSFETs. Depending on the proximity of the SiGe to the channel and the Ge content, 500-900 MPa stress is created in the channel [Mohta05]. Using this technique impressive saturation drain current enhancement up to 20%-25% have been demonstrated for p-channel MOSFETs [Thompson04,Zhang05]. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-channel MOSFET, which enhanced the drive current by 10% [Thompson04].

Alternatively, a less complex technique was jointly developed by AMD and IBM [Yang04]. Compressive and tensile capping layers grown on top of the transistors were used as local stressors instead of epitaxial films in the source and drain region [Pidin04,Sheraw05]. Si nitride (Si$_3$N$_4$) was found to produce either tensile or compressive strain depending on its deposition conditions. During the process, a highly tensile Si nitride layer is first deposited using thermal chemical vapor deposition over the entire wafer. This layer is afterwards etched away selectively from the p-MOS active areas. A compressive Si$_3$Ni$_4$ layer is then deposited using plasma-assisted chemical vapor deposition. Then the nitride layer on the n-channel transistors is etched away, resulting in wafers with n-channel transistors under tensile and p-channel transistors under compressive uniaxial strain. This dual stress liner (DSL) approach resulted in drive current enhancement of 11% (20%) for n-channel (p-channel) MOSFETs [Yang04].

In future CMOS technology nodes various strain techniques may be combined to yield even larger strain levels, as shown in Figure 2.3. P-channel MOSFETs with selective SiGe epitaxial layers providing compressive strain, and n-channel MOSFETs that are uniaxially strained by tensile cap films have been successfully combined on the same wafer recently [Jan05]. An optimized stress integration on SOI CMOS was presented by [Horstmann05], where an embedded SiGe process and a compressively stressed liner film were used to induce compressive strain in the p-channel MOSFET, whereas a stress memorization process and a tensile stressed liner film were used to induce tensile strain in the n-channel MOSFET. With optimization, the different stress techniques were shown to be highly compatible and additive to each other, improving p-channel and n-channel MOSFET saturation drive current by 53% and 32%, respectively.

Subsections

• 2.3.1 Hybrid Orientation Technology

E. Ungersboeck: Advanced Modelling Aspects of Modern Strained CMOS Technology