2.3.1 Gate Recess and Surface Treatment

The first E-mode transistor, reported back in 1996 by Khan et al. [15], was achieved by using thin AlGaN barriers. Endoh et al. [40] relied on thin AlGaN layer too. However, the device worked only in a very narrow drain-source voltage $V_\ensuremath {\mathrm {DS}}$ region. Liu et al. [41] could overcome this issue by substituting AlGaN for AlInGaN and also reach higher threshold voltage $V_\ensuremath {\mathrm {th}}$, however the maximum drain current $I_\ensuremath {\mathrm {D}}$ and transconductance $g_\ensuremath {\mathrm {m}}$ decreased.

A similar approach was adopted by other groups [42,43,17,44], who introduced Induced Coupled Plasma Reactive Ion Etching (ICP-RIE) in order to etch the AlGaN barrier. This technique was also used by Okite et al. [45] and Lanford et al. [46]. However, dry etching has low selectivity and results in a high concentration of defects and thus a high gate-leakage. In order to cure the damage, thermal annealing is required. Some of the metal stacks used for the gate contacts are incompatible with the high annealing temperatures. Therefore, the annealing has to be performed before the gate deposition. As the resist layer has to be removed, self-centered gate metal deposition is not possible. A second annealing step is required after the gate metal deposition in order to improve the Schottky barrier [47]. Cai et al. [16] demonstrated fluoride-based plasma treatment, which introduces fluoride ions in the barrier. Those raise the potential of the AlGaN barrier and the 2DEG channel. As no recess is required, damage to the AlGaN layer is avoided. This approach was further applied to double hetero-junction HEMTs (DH-HEMTs) [48] and used in combination with the gate recess technique [49]. All those approaches offer an optimization of the parameters ( $V_\ensuremath {\mathrm {th}}$ and $g_\ensuremath {\mathrm {m}}$) of selected devices on the same wafer.

Very thin AlGaN barrier layers have also been demonstrated to significantly rise the threshold voltage [50,51]. Devices fabricated using this technique are particularly well-suited for high-voltage applications due to the demonstrated high breakdown voltage.