Several groups have studied the high-temperature DC operation of AlGaN/GaN HEMTs on different substrates (sapphire [372,373,374], SiC [373], and Si [374,350]). AC measurements at elevated temperatures, however, are sparse: e.g. the temperature dependence of the cut-off frequency is compared to that of the transconductance by Akita et al. [375]. An investigation of the influence of high temperature on the microwave power performance of AlGaN/GaN HEMTs is conducted by Arulkumaran et al. [376].
The theoretical studies of GaN-based transistors at higher temperature are also rare. There are few analytical models developed [377,378,379], however, those are tailored for use in circuit simulation, not for device optimization. To our knowledge there is only one work which focuses solely on high-temperature HEMT device simulation [380], however, it relies on dated experimental data [375] and does not feature AC performance.
Based on the temperature dependent material and model parameters as
discussed in Chapter 4, the simulator is calibrated with the
structure (Device C in the previous section) serving as a calibration
device [15]. HD electron mobility Model B is chosen for this study. The
already mentioned values for the interface charges
(Table 5.1) are retained, as are the other material and
model parameters as e.g. the Schottky barrier height. However, it
should be mentioned that the changes in the barrier height with
temperature (in the range under investigation) are found to be
negligibly small [381].
Using the same set of models and model parameters a
benchmark
device is simulated. All other device properties (layer thickness and
composition and geometry) are the same. The ambient temperatures at
which the devices were measured and are simulated are 300 K, 365 K, and
425 K. For the gate-variation study, two more devices with
and
are simulated. Also a fourth ambient temperature of 485 K is
explored.
Using the values for the polarization-induced interface charges
from Table 5.1 a very good agreement between measurement
data and simulation results for the transfer characteristics of the
calibration device is achieved (Fig. 5.12). Our setup
allows for a proper modeling of the drain current also at elevated
temperatures. As an example, Fig. 5.13 shows the output
characteristics at 425 K. Two curves are shown for
=2 V: without
self-heating, which greatly overestimates the current; with
self-heating, which delivers a significantly better match, but
requires a higher computational effort. While
others [382] have observed a significant threshold
voltage (
) shift, in our measurements such a shift is
almost non-existent. As
depends on the carrier density,
carrier trap density and the Schottky barrier
height [383], we can assume that trapping effects in
the devices are also temperature-independent in this range (the
carrier density change is also negligible).
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Fig. 5.14 shows the lattice temperature in the device at
=20 V and
=2 V bias. The area where the lattice is heated
from high-energy electrons, is the high-electric field region under the
drain side of the gate and the gate-extension.
The same simulations are performed for the benchmark device. Retaining the same interface charge values, a good prediction of the threshold voltage is obtained (Fig. 5.15). Raising the ambient temperature, once again yields a good agreement between simulation results and experimental data, also for the output characteristics (shown at 425 K in Fig. 5.16).
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The RF device performance is studied by small-signal AC analysis
[365]. Fig. 5.17 shows the current gain
for the 0.25
m device for three temperatures. The gain
decreases for higher temperatures and the simulation agrees well with
the measurements. The calculated cut-off frequency
is compared to
the measured one in Fig. 5.18. In order to account for the
parasitics introduced by the measurement equipment the intrinsic
parameters delivered by the simulation are transformed into extrinsic
ones by using a standard two-port pad parasitic equivalent circuit. The
values of the circuit elements are listed in Table 4.15. As
already mentioned the measured device has two gate fingers of 50
m
width each, which leads to a higher gate capacitance due to
three-dimensional parasitic effects, than the simulated single device
with
=100
m.
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A very good agreement between measured and simulated S-parameters is
achieved at all temperatures both for the calibration device
(
) and the benchmark device
(
). Fig. 5.19 and Fig. 5.20
compare the simulated and measured intrinsic S-parameters in the range
100 MHz
26 GHz at
=7 V and
=260 mA/mm for the
HEMT at 300 K and 425 K. Fig. 5.21 and Fig. 5.22
compare predictive simulation results for the
device in the
same frequency range,
=7 V, and
=130 mA/mm at 300 K and
425 K.
The geometry of the transistors is pointed out to be an important factor
for high-temperature operation. Consequently, several authors have
studied the reduction of
with rising temperature for different
gate lengths e.g. [350,349]. There is agreement that for
short channel devices (
<
m) the carriers under the gate
travel with saturation velocity. Therefore, the decrease of
is
lower, because the decrease of the velocity in the saturation region is
also lower. While only submicron devices are studied, the results for
structures agree well (Fig. 5.23) with the ones
presented by Tan et al. [350]. However, for very small
gates an even lower temperature dependence is observed. The same effect
is more pronounced for the normalized
, where the devices
with
deliver a similar reduction of
with
temperature, while
of the sub-quartermicron devices decreases less
(Fig. 5.24). We believe that for such gate length, not only
but also the gate-drain and gate-source distances and the
exact geometry gain on importance, as for small gate lengths the
parasitic contributions have to be scaled according to typical scaling
rules in order to harvest the high-speed performance. In this case the
relative contributions of the ohmic elements and thus their temperature
dependence are reduced.
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