5.2.1 Recessed Gate

In order to analyze the trade-off between high-frequency performance and threshold voltage achieved by the gate recess technique [42], results from two-dimensional hydrodynamic simulations supported by experimental data [44] are presented [393].

AlGaN/GaN DHEMT and EHEMT structures with T-gates of 250 nm length share the same layer specification and are processed on the same SiC wafer. The devices consist of GaN buffer, 22 nm thick Al $_{0.22}$ Ga $_{0.78}$ N (Al $_{0.18}$ GaN $_{0.82}$ N for the EHEMT device) barrier layer, 3 nm thick GaN cap layer, and SiN passivation (Fig. 5.46). The cap and part of the barrier layer under the gate of the EHEMT are recessed by Cl

plasma etching. A remaining AlGaN barrier thickness t $_\ensuremath{\mathrm{bar}}\approx$ 11 nm is assumed. The Ohmic contacts are assumed to reach the 2DEG in the channel.

**Figure 5.46:** Schematic layer structure of the recessed device.
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The densities of the polarization charges at the channel/barrier interface and at the barrier/cap interface are determined by calibration against the experimental data to be 9 $\times$ 10 $^{12}$ cm $^{-2}$ and $-2\times$ 10 $^{12}$ cm $^{-2}$ , respectively. Low Ohmic contact resistances of 0.2 $\Omega$ mm are considered [44]. Self-heating effects are accounted with a substrate thermal contact resistance of R $_\ensuremath{\mathrm{th}}$ =5 K/W. This value lumps the thermal resistance of the nucleation layer and the substrate.

5.2.1.1 Simulation Results

Fig. 5.47 compares the simulated transfer characteristics to experimental data. Both devices are simulated using the same set of models and model parameters, including the interface charge densities. A good agreement is obtained, both for the threshold voltage and the transconductance $g_\ensuremath {\mathrm {m}}$ (Fig. 5.48).

**Figure 5.47:** Transfer characteristics at $V_\ensuremath {\mathrm {DS}}$ =7 V: lines - simulation, symbols - experimental data.
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**Figure 5.48:** Transconductance $g_\ensuremath {\mathrm {m}}$ at $V_\ensuremath {\mathrm {DS}}$ =7 V: lines - simulation, symbols - experimental data.
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The mismatch between the drain current at high gate voltages is due to the high gate leakage current in the real device, for which the simulation does not account. A possible explanation for the underestimation of the peak $g_\ensuremath {\mathrm {m}}$ for the recessed device is an overestimation of the sheet resistance under the gate. Simulated output characteristics for both structures are compared to measurements in Fig. 5.49 and Fig. 5.50.

**Figure 5.49:** Comparison of DHEMT output characteristics, $V_\ensuremath {\mathrm {GS}}$ stepping 0.5 V.
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**Figure 5.50:** Comparison of EHEMT output characteristics, $V_\ensuremath {\mathrm {GS}}$ stepping 0.5 V.
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The RF simulations provide slightly higher cut-off frequency $f_\ensuremath {\mathrm {t}}$ than the experiments for both structures (Fig. 5.51). Note, that both the measured and simulation data show an increase of $f_\ensuremath {\mathrm {t}}$ and $f_\ensuremath{\mathrm{max}}$ for the EHEMT structures.

**Figure 5.51:** Comparison of the cut-off frequency $f_\ensuremath {\mathrm {t}}$ : symbols - simulation, lines - experimental data.
$\includegraphics[width=9.7cm]{figures/sim/rec/FtSGl.eps}$

Since the gate capacitance depends on the gate channel distance, several simulations are performed with variable recess depths, which means a variable barrier thickness t $_\ensuremath {\mathrm {bar}}$ under the gate. As expected a shift in the threshold voltage is observed (Fig. 5.52) and $g_\ensuremath {\mathrm {m}}$ increases with decreasing t $_\ensuremath {\mathrm {bar}}$ (Fig. 5.53) due to the lack of charge control for thicker layers.

**Figure 5.52:** Simulated transfer characteristics for devices with different barrier thickness t $_\ensuremath {\mathrm {bar}}$ under the gate.
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**Figure 5.53:** Simulated transconductance for devices with different barrier thickness t $_\ensuremath {\mathrm {bar}}$ under the gate.
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However, the simulated $f_\ensuremath {\mathrm {t}}$ characteristics do not show any noticeable change (Fig. 5.54). Fig. 5.55 shows the gate source capacitance which increases with decreasing t $_\ensuremath {\mathrm {bar}}$ . It compensates the increase in $g_\ensuremath {\mathrm {m}}$ , thereby resulting in a constant $f_\ensuremath {\mathrm {t}}$ . Thus, the major reason for the rise of $f_\ensuremath {\mathrm {t}}$ and $f_\ensuremath{\mathrm{max}}$ of EHEMTs in comparison to DHEMTs (Fig. 5.51) is the absence of barrier/cap negative interface charges under the gate. The exact depth of the recess has less influence on $f_\ensuremath {\mathrm {t}}$ and $f_\ensuremath{\mathrm{max}}$ , but has a significant impact on the threshold voltage and the transconductance.

**Figure 5.54:** Simulated cut-off frequency for devices with different barrier thickness t $_\ensuremath {\mathrm {bar}}$ under the gate.
$\includegraphics[width=10cm]{figures/sim/rec/FtSGvarl.eps}$

**Figure 5.55:** Simulated gate-source capacitance for devices with different barrier thickness t $_\ensuremath {\mathrm {bar}}$ under the gate.
$\includegraphics[width=10cm]{figures/sim/rec/C11varl.eps}$