), because the floating gate polysilicon must be fairly thick to provide an acceptable coupling ratio between the floating gate and the control gate, which does not apply to SONOS gate stacks. Thus, step coverage is alleviated and the number of necessary masks and processing steps can be reduced in comparison to floating gate cells.
Another limiting factor for floating gate cells is the height of the ONO gate stack (reduction of the tunnel oxide leads to an increased leakage from the polysilicon). The estimated scaling limit for floating gate cells is at the
technology node, due to electrical interference between adjacent cells, caused by the electric field of the electrons stored in the ploysilicon layer[37].
SONOS gate stacks offer a higher quality charge storage due to the smooth homogeneity of the nitride film compared to the polycrystalline film of floating gate stacks and are less prone to oxide defects. Because of the insulating nature of the nitride film, an occurring leakage path is locally confined and only able to empty a few traps. Therefore, Stress Induced Leakage Current (SILC) should not be a big issue, (i.e. the generation of traps within the oxide's band gap, enabling trap-assisted tunneling and leading to a discharge of the floating gate.[38]). In comparison to floating gate technology, SONOS is not susceptible to drain turn-on and floating gate interference and also insensitive to SILC, when the bottom oxide layer is thinner than in the floating gate technology, thus, enabling faster programming and lower write/erase voltages. However, there are also disadvantages: The trap related reliability issues are not fully understood and there is an erase saturation which can lead to a permanent logic ''1`` state, rendering the cell useless.