2.1.3 Scaling of Floating Gate and SONOS

In the present floating gate technology node, the control gate wraps around the floating gate, which serves as the necessary electrical coupling for the operation of the device. Applying an external voltage at the CG induces a voltage drop between the tunnel dielectric and the $Si$ substrate. Depending on the amount of the applied voltage, the charge stored in the FG can be sensed (read out) or electrons can tunnel through the dielectric (program/erase) at higher voltages.

Further scaling of the feature size will lead to a modification of the device structure due to the lack of physical space between neighboring cells. This will cause a planarization of the device and a degradation of the coupling factor. To compensate the loss of the coupling capacitance of the sidewalls two approaches are considered. Firstly, by exchanging the Inter Poly Dielectric (IPD) with a high-k material the gate coupling factor is increased and secondly, by replacing the flash ONO gate stack by a SONOS charge trapping gate stack, facilitates a thinner gate stack. For charge trapping devices also high-k materials are needed as Blocking Oxides (BOs) between the trap layer and the control gate (Fig. 2.4). Both applications require high-k materials with large band gaps and band offsets, limiting the materials to choose and restricting the k-values in the moderate range from $\sim9$ to $20$[39]. Due to the charge retention specifications for flash-based memory ($\sim15$ years) very low leakage through IPD or the BO is needed. Therefore, the trap density of the high-k dielectric should be as low as possible.

$Al_{2}O_{3}$ with ($k\sim9$) is a possible candidate for replacing $SiO_{2}$ as IPD and BO in the near future. A substantial improvement in device characteristics for crystalline $Al_{2}O_{3}$ compared to amorphous $Al_{2}O_{3}$ has been reported [40]. At $\sim850\mathrm{C}^{\circ}$ $Al_{2}O_{3}$ crystallizes into the $\gamma-Al_{2}O_{3}$ phase, increasing its band gap and band offsets, and localizing its defects in a horizontal band between $1.7\,\mathrm{eV}$ and $2.0\,\mathrm{eV}$. However, the properties of the $Al_{2}O_{3}$ films (crystallization, texture, and microstructure) have been found to depend strongly on the deposition technique and parameters.

While for the next technology node $Al_{2}O_{3}$ with a $TiN$ metal control gate may be sufficient, future generations demand higher even $k$-values. Therefore, several dielectrics with higher $k$-values ($12-30$) are under investigation. The improvement in $k$-values must not be at the expense of a reduced band gap or increased trap density. Promissing candidates are aluminates and scandates. For instance, the rare earth scandates $DyScO$ and $GdScO$ feature higher $k$-values compared to $Sc_{2}O_{3}$, while maintining at the same time the band gap ( $6\,\mathrm{eV}$) and band offset ( $\sim 2\,\mathrm{eV}$ with respect to $Si$) over a wide range of compositions. Aluminates such as $H\!f\!AlO$ and rare earth aluminates $REAlO$ (e.g. $LaAlO$) inherit a band gap of $\sim6\,\mathrm{eV}$ for their amorphous phase, and are close to amorphous $Al_{2}O_{3}$for a wide compositional range, but exhibit a lower than crystalline $Al_{2}O_{3}$. Also their band offsets remain independent over a wide compositional range and stay close to amorphous $Al_{2}O_{3}$. Additionally, the permittivities of amorphous $H\!f\!AlO$ and $LaAlO$ vary approximately linearly with composition ($\sim14$ for $LaAlO$, and $\sim16$ for $H\!f\!AlO$ at an $1:1$ ratio) [39].

However, also for floating gate devices the interfacial properties are of great importance. Govoreanu et al. [41] investigated various top gate materials ($TiN$, $TaN$, and $n^{+}$-poly-$Si$) and different processing procedures and found for the used $SiO_{2}$-$H\!f\!AlO$ IPD ( $1\,\mathrm{nm}$ and $12\,\mathrm{nm}$ respectively) the $SiO_{2}$ layer as a limiting element for the achievable program window, due to shallow traps and their interaction with the $H\!f\!AlO$ as parasitic Variable Oxide Thickness (VARIOT) gate stack.

Potentially better suited to build ultra-scaled devices are approaches like storing the information in a silicon nanocrystal layer instead of a nitride layer [42,43]. Silicon nanocrystal memories show no erase saturation for small tunnel oxide thickness, deeper electron storage traps ( $\sim3\,\mathrm{eV}$), extra local field effects as well as Coulomb blockade (essential to superior Fowler-Nordheim erase characteristics compared to SONOS). The device variability due to the variation of crystal size and distance is not critical due to partial selfordering [44]. Ohba [45] demonstrated a $10\,\mathrm{nm}$ bulk-planar SONOS type memory with a double tunnel junction, exhibiting good scalability while offering low write/erase voltages and excellent charge retention characteristics at the same time. There are additionally FinFET architectures in SONOS and nanocrystal devices, indicating a promising path way [46], and investigations for quantum dot materials different to silicon [47].