4.5.1.2 UMOSFET Simulation

Fig. 4.17 and 4.18 show the on-state characteristics for a constant gate-to-source voltage (V $_\mathrm{GS}$ ) as a function of the drain-to-source voltage (V $_\mathrm{DS}$ ), and the transfer characteristics as a function of the applied V $_\mathrm{GS}$ for a constant V $_\mathrm{DS}$ at two different lattice temperatures. For any fixed gate voltage above threshold (V $_\mathrm{GS}$$>$V $_\mathrm{T}$ ),

Figure 4.17: On-state characteristics (left), and transfer characteristics (right) of a UMOSFET at room temperature.

Figure 4.18: On-state characteristics (left), and transfer characteristics (right) of a UMOSFET at 500 K.

the on-state current and the transistor gain (dI $_\mathrm{D}$/dV $_\mathrm{G}$) is larger at room temperature than at 500 K due to the decrease in carrier (channel electron) mobility with temperature. As the gate voltage is decreased, the channel current decreases because there are fewer electrons attracted into the channel to carry current. The threshold voltage which is V $_\mathrm{T}$=5V, as seen in Fig. 4.17 (right) at room temperature, decreases slightly with temperature, see Fig. 4.18 (right) for temperature of 500K. As the gate voltage is decreased below threshold (V $_\mathrm{GS}$$<$V $_\mathrm{T}$), electrons are repelled from the oxide-semiconductor interface effectively turning off current flow in the channel. As the temperature is increased well above room temperature,

Figure 4.19: The carrier mobility at 300K (left) and 500K (right) of UMOSFET in 6H-SiC at V $_\mathrm{DS}$=5 V and V $_\mathrm{GS}$=10 V.

Figure 4.20: On-state (left), and transfer characteristics (right) as a function of temperature.

the ability of carriers to move through a semiconductor crystal is decreased. This arises because atoms in the crystal lattice have more thermal energy that results in more collisions with carriers moving through the crystal in response to an electric field. The resulting decrease in carrier mobility with temperature due to lattice scattering reduces the amount of current that a transistor can carry (see Fig. 4.19). In general, the increase in the semiconductor device resistance with temperature follows a $T^x$ power law behavior, where $x$ is usually between 1.5 and 2.5 for $\alpha$-SiC well above room temperature where lattice scattering is dominant. An illustration of the effect of the temperature on the on-state and transfer characteristics is depicted in Fig. 4.20.

The reverse voltage characteristics depicted in Fig. 4.21 (left) shows the blocking voltage of 1700V at room temperature which slightly increases with rising temperature. It is approximately 85 $\%$ of the theoretical plane-junction blocking voltage for the designed blocking layer. The specific on-resistance determined from the linear region of the IV curve is 23.12 m$\Omega$cm$^2$ and results in a $V^2_\mathrm{B}/R_\mathrm{on,sp}$ FOM of 125MW/cm$^2$. Fig. 4.21 (right) summarizes the effect of the temperature on the leakage current and the specific on-resistance on this device. The $R_\mathrm{on,sp}$ value increases with temperature despite the negative shift of the threshold voltage (V $_\mathrm{T}$), due to the decrease in the electron mobility in the drift region.

The sharp geometry of the trench corners in the UMOSFET give rise to two-dimensional field crowding as shown in Fig. 4.22 in the blocking state, resulting in high fields in the oxide. This is especially critical in SiC, since the critical field for avalanche breakdown in SiC is approximately ten times higher than in silicon, the peak surface fields in the semiconductor can reach values in the range of 2-3 MV/cm without initiating semiconductor breakdown. By GaußLaw, the field in the oxide is some 2.5 times higher than the field in the adjacent SiC. This can bring the oxide field to 5-7 MV/cm, very close to the breakdown field of the oxide. With a two to three times enhancement in field at the trench corners, oxide breakdown is likely to occur soon. Oxide breakdown at the trench corners thus becomes the factor limiting the blocking voltage of SiC UMOSFETs.

Figure 4.21: Reverse bias characteristics of a UMOS power transistor in SiC (left), and the effect of temperature on the specific-on-resistance and leakage current (right).

Figure 4.22: Electric field profile in the trench area for a 1500 V reverse biased UMOSFET (left), and the peak field crowding at the trench corner in a three dimensional representation (right).

T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation