4.5.1.1 UMOSFET Structure

Fig. 4.16 illustrates the basic design used for power UMOSFETs in SiC. The UMOS design, in its most basic form, requires no ion implantation or implant annealing steps, and was the first power MOSFET realized in SiC [179].
Figure 4.16: Cross section of a UMOS power transistor in SiC.
\includegraphics[width=0.5\linewidth]{figures/umosfet.eps}
The UMOSFET suffers from several practical problems, however. First, the MOS channel lies along the vertical sidewall of a trench formed by RIE (see Section 2.6). Depending upon the precise crystal alignment, this sidewall may approximate the (11$ \Bar{2}$0) or the (1$ \Bar{1}$00) crystal planes, or may lie along an intermediate direction. Current flow in the channel is parallel to the c-axis of the crystal and carriers must cross alternating silicon and carbon planes of the crystal. The a-axis MOS interface includes bonds between oxygen atoms and both silicon and carbon surface atoms, giving rise to new and as-yet poorly understood electrical characteristics (interface traps and interface charges). Surface roughness due to RIE damage is present, but not yet fully quantified. All these factors contribute to a lower inversion layer mobility on these surfaces.


For this simulation analysis, a 6H-SiC based UMOSFET was selected owing to its high breakdown field, and it was the first polytype of SiC used for this device structure. The device is designed for a blocking voltage of 2000V. The corresponding blocking layer thickness and the concentration were selected from Fig. 4.4 as 10 $ \mu$m and 1.5$ \times$10$ ^{16}$cm$ ^{-3}$, respectively. The gate length and oxide thickness were optimized to be 0.9 $ \mu$m and 50nm.

Table 4.4: Summary of optimized device parameters used for the simulation of a UMOSFET.
parameter value
gate oxide thickness and channel length 50 nm, $ 0.9\,\mathrm{\mu}$m
drift layer thickness and concentration $ 10\,\mathrm{\mu}$m, 1.5 $ \times10^{16}$ cm $ ^{-3}$
p-base thickness, length and concentration $ 1.2\,\mathrm{\mu}$m, $ 3.0\,\mathrm{\mu}$m, $ 1.0\times
10^{17}$ cm$ ^{-3}$
n+ source thickness, length and concentration $ 0.3\,\mathrm{\mu}$m, $ 2.0\,\mathrm{\mu}$m, $ 1.0\times10^{19}$ cm$ ^{-3}$


T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation