Fig. 4.16 illustrates the basic design used for power UMOSFETs in SiC. The UMOS
design, in its most basic form, requires no ion implantation or implant annealing steps, and
was the first power MOSFET realized in SiC [179].
Figure 4.16:
Cross section of a UMOS power transistor in SiC.
The UMOSFET suffers from several practical problems, however. First, the MOS channel lies
along the vertical sidewall of a trench formed by RIE (see
Section 2.6). Depending upon the precise crystal alignment, this sidewall
may approximate the (110) or the (100) crystal planes, or may lie along an
intermediate direction. Current flow in the channel is parallel to the c-axis of the crystal
and carriers must cross alternating silicon and carbon planes of the crystal. The a-axis MOS
interface includes bonds between oxygen atoms and both silicon and carbon surface atoms,
giving rise to new and as-yet poorly understood electrical characteristics (interface traps
and interface charges). Surface roughness due to RIE damage is present, but not yet fully
quantified. All these factors contribute to a lower inversion layer mobility on these
surfaces.
For this simulation analysis, a 6H-SiC based UMOSFET was selected owing to
its high breakdown field, and it was the first polytype of SiC used for this device
structure. The device is designed for a blocking voltage of 2000V. The corresponding blocking
layer thickness and the concentration were selected from Fig. 4.4 as 10 m
and 1.510cm, respectively. The gate length and oxide thickness
were optimized to be 0.9 m and 50nm.
Table 4.4:
Summary of optimized device parameters used for the simulation of a
UMOSFET.