Next: 2.3 External Mechanical and
Up: 2. Strained Si Technology
Previous: 2.1 Substrate Strain
Subsections
To overcome these problems associated with substrate strain, a new approach
based on uniaxial strain created through processing steps was suggested. This
approach provided the semiconductor industry the knob to improve the
performances of the nMOS and pMOS devices independently.
In conventional CMOS process flows, stress patterns can arise from various
factors such as different processing temperatures, difference in thermal
expansion coefficient, different growth conditions and mechanisms, and dopant
implantations. The distribution of these process-induced stresses can be highly
non-uniform and can result in larger values of strain in certain parts of the
device than in others. Thus it is possible to engineer an almost uniaxial
stress into the Si channel beneficial for mobility enhancement. Another
advantage of uniaxial stress over biaxial stress is that it can be induced by a
process step which is much easier to incorporate into the CMOS fabrication with
negligible additional costs. However, these process-induced stresses are
strongly dependent on the device layout and therefore care should be taken to
ensure that the uniaxial stress components along different directions add
complementarily and are not canceling each other out.
In this technique, strain is introduced into the MOSFET channel through the use
of capping layers [Ito00]. The capping layers usually of Si nitride
(SiN) can be grown using chemical vapor deposition techniques after the
conventional salicide formation, and can produce compressive or tensile stress
depending on the deposition conditions. It has been demonstrated how a highly
tensile stressed SiN layer improves the nMOS
performance [Shimizu01]. However, since stress has different impact on
electrons and holes, both compressive and tensile stress are required for
enhancing the performance of CMOS transistors: tensile for nMOS and compressive
for pMOS.
CMOS architectures in which both compressive and tensile stress can be used in
conjunction have been suggested. In this dual stress liner technology (DSL), a
tensile SiN layer is deposited over the entire wafer, followed by
patterning and etching the film off the pMOS transistors. Afterwards, a
compressive film is deposited and is etched off the nMOS transistors. Thus the
performance of the nMOS and pMOS devices can be improved
simultaneously. Improvements in both the linear as well as the saturation drain
currents have been reported [Yang04,Pidin04].
SiN capping layers could alternatively be used for straining the
channel through a stress memorization technique (SMT) [Chen04]. Drain
current improvements greater than 15% have been reported using SMT for nMOS
devices [Chan05]. In this approach, the polysilicon-gate of the nMOS
transistor is amorphized by implantation using heavy atoms such as Ge or As,
followed by the tensile nitride layer deposition. The poly-gate is next allowed
to recrystallize during source-drain annealing after which the capping layer is
removed. It is believed that the poly-Si gate memorizes the stress during
the recrystallization process which is retained even after the removal of the
capping layer.
The LOCOS (local oxidation of Si) technology used for isolation was replaced
by shallow trench isolation (STI) for deep submicron technologies. However,
with the further scaling of CMOS devices, the distance between STI and channel
decreases which induces stress into the channel. Since the stress resulting
from STI is compressive, it is found to be detrimental for nMOS
devices [Scott99,Ootsuka00]. The situation can however be improved by
recessing the STI [STI07] which relieves the compressive stress in the
channel. Moreover, it has been shown that with optimized fabrication steps, the
mobility of the pMOS devices can be enhanced using STI
stress [Sanuki03].
The lattice mismatch between Si and SiGe could also be used for producing
uniaxial compressive stress in the channel. This can be accomplished by first
etching a recess into Si, followed by epitaxially growing SiGe into the
source and drain regions of the pMOS devices. The lattice mismatch between the
SiGe source and drain regions and the Si channel introduces a compressive
stress into the channel. This results in an improved hole mobility with the
mobility enhancement factor dependent on the amount of strain coming from the
Ge content in the SiGe. For 17% Ge content, that amounts to approximately 1%
strain, mobility enhancements greater than 50% have been
reported [Thompson04]. Similar mobility enhancements can be obtained for
electrons by introducing tensile stress into the nMOS channel by employing
selective SiC heteroepitaxy for the source and drain regions [Ang05].
The different mechanisms of generating process-induced stress are illustrated
in Fig. 2.4.
Figure 2.4:
Various techniques of introducing process-induced uniaxial stress into
the channel. The techniques include stress liners, stress from STI and
heteroepitaxial stress.
Next: 2.3 External Mechanical and
Up: 2. Strained Si Technology
Previous: 2.1 Substrate Strain
S. Dhar: Analytical Mobility Modeling for Strained Silicon-Based Devices