next up previous contents
Next: 7.1 Power MOS Devices Up: Dissertation Robert Entner Previous: 6.6 The New Model


7. Case Studies

IN this chapter the effect of negative bias temperature instability on device and circuit performance is investigated. For this purpose the multi-dimensional device- and circuit simulator Minimos-NT [44] is used. As part of this work it has been extended by new models and capabilities to simulate and visualize the degradation mechanisms and their effects.

The calibration task has been performed using the gate oxide of a high voltage MOSFET as reference. The device has been stressed with different temperatures allowing the calibration of the full set of NBTI model parameters. To investigate the degradation at circuit level a CMOS inverter, a 6 transistor SRAM cell, and a five stage ring oscillator are simulated including their susceptibility to NBTI based degradation.



Subsections
next up previous contents
Next: 7.1 Power MOS Devices Up: Dissertation Robert Entner Previous: 6.6 The New Model

R. Entner: Modeling and Simulation of Negative Bias Temperature Instability