Abstract

Topography simulations allow for a visualization of semiconductor surfaces as well as the interfaces between various material regions after a given processing step. Topography modeling of well-established processing techniques, such as material etching and deposition, has been studied for decades and very sophisticated models exist which envision the semiconductor surfaces and interfaces using the Level Set method. However, as the technology node shrinks along the predicted path of Moore's law, novel processing techniques are constantly introduced in order to enable miniaturization and to ease the financial burden of processing at these reduced nodes.

The ability to simulate semiconductor wafer topographies after the application of newly-introduced process technologies can go a long way in understanding their potential. The local anodic oxidation of silicon surfaces with an atomic force microscope (AFM) is a method which produces nanosized patterns on a silicon wafer using a localized charged needle. The technology has been developed in order to tackle the limited miniaturization potential of current photolithographic techniques. In the scope of this work, a technique which models the changing silicon topography as the silicon dioxide pattern is applied to the wafer is introduced. The topography motion is simulated using a Monte Carlo technique, whereby a particle distribution follows the surface charge density distribution. The charge density arises from the application of a strong electric field between the AFM needle tip and the silicon wafer surface.

Similarly, EEPROM memory cells can not be miniaturized further with the current processing techniques. Therefore, three-dimensional structures are being introduced in order to increase the number of available memory cells without increasing the area required. In the scope of this work, a model for Bit Cost Scalable (BiCS) memory hole etching is implemented in a Level Set framework as a combination of silicon and silicon dioxide etching steps.

A spray pyrolysis deposition model is also developed and implemented within the Level Set framework. This processing technique enables the deposition of thin films for applications such as gas sensors and solar cells. Two models for the topography modification due to spray pyrolysis deposition are presented, with an electric and a pressure atomizing nozzle. The resulting film growth is modeled as a layer by layer deposition of the individual droplets which reach the wafer surface or as a CVD-like process, depending on whether the droplets form a vapor near the interface or if they deposit a film only after surface collision.